How Many Color Planes Does VGA Hardware Use?

The classic Video Graphics Array (VGA) hardware architecture uses 4 color planes (Planes 0 through 3) in its native physical memory arrangement. Introduced by IBM in 1987 with the PS/2 series, the standard 256 KB VGA frame buffer is structured as four parallel 64 KB memory banks. Understanding how these planes interact with display modes, CPU memory windows, and internal shift registers is central to grasping how legacy PC graphics functioned.

The Physical Architecture of VGA Memory

A standard VGA adapter contains 256 KB of video RAM. Rather than organizing this memory in a single flat, linear block—which would exceed the real-mode 64 KB or 128 KB memory windows accessible through the PC's memory map—IBM split the RAM across four 64 KB parallel planes:

• Plane 0: Typically holds Blue channel data or lower-order intensity bits.
• Plane 1: Typically holds Green channel data.
• Plane 2: Typically holds Red channel data (and character font definitions in text modes).
• Plane 3: Typically holds Intensity data or attribute bits.

Because all four planes occupy the exact same base address range in the host CPU address space (most commonly 0xA0000 to 0xAFFFF), specialized hardware registers—specifically the Sequencer and the Graphics Controller—determine how reads and writes route to and from the individual planes.

Planar Organization in 16-Color Graphics Modes

The four-plane design is most clearly visible in the standard 16-color graphics modes, such as Mode 12h (640×480 resolution, 16 colors) and Mode 0Eh (640×200 resolution, 16 colors).

In these modes, each pixel's color is represented by a 4-bit index into a palette register (\(2^4 = 16\) possible colors). Instead of packing these 4 bits together inside one byte of system memory, the bits are distributed across the four planes:

1. Bit 0 of the pixel index resides in Plane 0.
2. Bit 1 of the pixel index resides in Plane 1.
3. Bit 2 of the pixel index resides in Plane 2.
4. Bit 3 of the pixel index resides in Plane 3.

A single CPU byte write to address 0xA0000 can update a specific bit across eight contiguous horizontal pixels simultaneously, provided the Graphics Controller's write mask and plane enable registers are configured to allow it.

Internal Registers and Memory Access Modes

Because four bytes share a single memory address, the VGA Graphics Controller provides specific read and write modes to manipulate the planes without requiring four separate bus transactions:

Write Modes

• Write Mode 0: The default mode where CPU data is rotated, logical operations are applied via latch registers, and the result is written across enabled planes.
• Write Mode 1: Directly copies internal 32-bit latched data (8 bits from each of the four planes) from a previous read into a new destination address, enabling fast planar screen-to-screen blits.
• Write Mode 2: Allows the host CPU to supply a 4-bit color value in the lower nibble of a byte. The hardware expands this value across all four planes for the targeted pixels.
• Write Mode 3: Combines expansion data with a bitmask, frequently used for fast patterned line drawing and font rendering.

Read Modes

• Read Mode 0: The CPU reads directly from one designated plane, selected via the Read Map Select Register.
• Read Mode 1: The CPU performs a color comparison. The VGA hardware evaluates all four planes simultaneously against a Color Compare Register and returns a byte where each bit indicates whether that pixel matched the comparison criteria.

How 256-Color Modes Use the Planes

In the famous Mode 13h (320×200 resolution, 256 colors), each pixel requires 8 bits (1 byte) to index into the 256-color DAC palette. While the programmer interacts with Mode 13h as if it were a linear array of bytes from 0xA0000 to 0xAFA00, the underlying hardware still contains only the four physical planes.

To accommodate this, the VGA hardware uses a mode known as "Chain-4":

• The lowest two address bits select the physical plane: Address modulo 4 determines whether a byte routes to Plane 0, 1, 2, or 3.
• Consecutive horizontal pixels are distributed cyclically across Plane 0, Plane 1, Plane 2, and Plane 3.
• The CPU address lines are shifted by two bits so each plane stores every fourth pixel.

While Chain-4 simplified programming by providing a linear memory abstraction, it wasted memory bandwidth and limited available video memory to 64 KB.

By disabling Chain-4, programmers unlocked "Mode X" (or unchained modes). In unchained 256-color modes, developers manually selected which plane to write to, allowing full access to all 256 KB of video memory for double buffering, page flipping, and hardware-accelerated planar operations.

Text Modes and Plane Allocation

The planar architecture also manages alphanumeric display modes, such as standard 80×25 text (Mode 03h):

• Plane 0: Stores ASCII character codes.
• Plane 1: Stores character attributes (foreground and background color combinations, blinking, and underline flags).
• Plane 2: Stores the font glyph bitmap patterns (up to eight distinct 256-character fonts can be loaded simultaneously).
• Plane 3: Remains unused in basic text display, or serves as extended attribute storage in specific custom configurations.