UEFI Memory Initialization Using Cache-as-RAM

Before system memory (DRAM) can be accessed, modern platforms face a classic chicken-and-egg dilemma: firmware needs working memory to execute the complex algorithms required to train and initialize the memory controller, but memory is not yet available. The Unified Extensible Firmware Interface (UEFI) solves this problem by using a mechanism known as Cache-as-RAM (CAR), or Temporary RAM (T-RAM). This article explains how UEFI leverages the CPU's internal cache during early boot phases, executes the Memory Reference Code (MRC), and transitions the system from temporary storage to fully initialized physical memory.

The Boot Dilemma: Running Code Without DRAM

In early boot stages, the CPU can execute code directly from non-volatile SPI flash memory via memory-mapped I/O (known as Execute-in-Place, or XIP). However, pure XIP is heavily constrained:

  • High-level programming languages like C require a read/write stack to manage local variables, function calls, and data structures.
  • Reading directly from SPI flash is slow and lacks writable temporary storage.
  • Modern DRAM technologies (DDR4, DDR5) require complex calibration—such as signal timing adjustments, voltage training, and topology detection—before they can reliably read or write a single byte.

Because assembly language is impractical for writing comprehensive memory training algorithms, UEFI must establish a temporary read/write environment before main memory is brought online.

Cache-as-RAM (CAR)

Cache-as-RAM transforms the CPU's on-die L1 or L2 data cache into a temporary, flat memory space. Because cache memory resides entirely within the processor core, it is functional immediately upon power-up and requires no external bus or chipset configuration.

To configure CAR, UEFI executes architecture-specific instructions during the Security (SEC) phase:

  1. Disabling Normal Cache Eviction: On x86 processors, the firmware configures the processor's Memory Type Range Registers (MTRRs). The cache lines covering a specific physical address range are designated as Write-Back (WB) memory.
  2. Setting "No-Eviction" Mode: The processor is configured to prevent dirty cache lines from being written out to the non-existent system bus (often referred to as No-Eviction Mode).
  3. Pre-loading Cache Tags: By executing specific reads or cache-invalidation commands, firmware pre-populates cache tags, essentially turning the high-speed cache into a software-accessible SRAM region.

Once configured, this temporary address space provides both a stack and an initial heap, allowing the CPU to transition from raw assembly code to compiled C code.

The Role of PEI and Memory Reference Code (MRC)

With CAR established, the platform hands control to the Pre-EFI Initialization (PEI) phase. The PEI Foundation uses the temporary memory to instantiate PEI Foundation services and dispatch PEI Modules (PEIMs).

The critical module responsible for memory bring-up is the Memory Reference Code (MRC):

  • Hardware Probing: The MRC reads Serial Presence Detect (SPD) data from the memory modules over the low-speed SMBus/I2C interface to determine the installed RAM's timing capabilities, capacity, and manufacturer specifications.
  • Controller Setup: The MRC programs the integrated memory controller (IMC) inside the CPU or system-on-chip (SoC).
  • Signal Training: The code executes training sequences to synchronize clock signals, calibrate impedance, and adjust data-eye margins across all memory channels.

All intermediate calculations, state machines, and data structures used during this complex calibration process reside entirely within the temporary Cache-as-RAM space.

Tearing Down CAR and Transitioning to DRAM

Once the MRC finishes training and successfully verifies that DRAM can reliably handle read and write operations, CAR is no longer required:

  1. Creating Handoff Blocks (HOBs): The PEI phase packages memory information, such as physical memory maps and discovered resources, into structures called Handoff Blocks.
  2. Stack and Heap Migration: UEFI copies the execution stack, HOBs, and critical global variables from the temporary CAR space into the newly initialized physical DRAM.
  3. Restoring MTRRs: The firmware flushes and resets the processor's MTRRs back to their normal operational state, re-enabling standard hardware caching semantics.
  4. Permanent Memory Handoff: The stack pointer is pointed to main memory, CAR is dismantled, and UEFI transitions to the Driver Execution Environment (DXE) phase, where the entire physical address space becomes available.