UEFI Drivers and Power Management Chip Interfaces

Modern computer platforms rely on Unified Extensible Firmware Interface (UEFI) drivers to configure, monitor, and regulate advanced power management chips—primarily Power Management Integrated Circuits (PMICs) and Embedded Controllers (ECs). This article explains how UEFI firmware establishes hardware-level bus communication with these chips, abstracts functionality through specialized firmware protocols, coordinates boot-time power rail sequencing, and dynamically builds the ACPI structures required to transfer power-state authority to the operating system.

Hardware Bus Communication

Advanced power management chips do not sit directly on high-speed memory-mapped buses like PCIe. Instead, they connect to the system chipset via low-pin-count serial interfaces such as I2C, SMBus, SPI, or eSPI (enhanced Serial Peripheral Interface).

To interact with a PMIC, the UEFI environment relies on a layered driver architecture:

  1. Host Controller Drivers: A low-level UEFI driver initializes the platform's bus master (e.g., an Intel or AMD I2C host controller).
  2. Bus Protocols: The host driver produces standard interfaces, such as the EFI_I2C_IO_PROTOCOL, which abstract read, write, and command-packet transmission.
  3. Target Device Drivers: The dedicated PMIC or EC driver consumes these generic bus protocols to read and write to the chip’s internal command and configuration registers.

Through these serial commands, the driver accesses specific chip registers that govern voltage regulators, current limits, battery monitoring, and platform thermal thresholds.

Boot Phase Responsibilities: PEI vs. DXE

Firmware communication with power hardware occurs across two primary UEFI phases:

  • Pre-EFI Initialization (PEI): During early initialization, memory has not yet been trained. Early power management drivers (PEIMs) execute from ROM or CPU cache to assert essential power rails, configure CPU core voltages (Vcore), and enable memory power (VDDQ). Without this step, main system memory cannot initialize.
  • Driver Execution Environment (DXE): Once main memory is online, DXE drivers manage more sophisticated power capabilities. At this stage, drivers establish dynamic voltage and frequency policies, configure fine-grained power sequencing, set charge rates, and prepare telemetry pathways.

The Role of UEFI Protocols

In the DXE phase, vendor-specific chip drivers register protocols in the UEFI core database to expose power functions to the rest of the firmware. For example, a custom PLATFORM_PMIC_PROTOCOL might expose functions such as SetVoltageRail(), GetBatteryStatus(), or SetLowPowerState().

Other modular firmware components, such as thermal management modules, display drivers, or CPU initialization code, call these protocols without needing to know the low-level bus address or register layout of the specific PMIC installed on the motherboard.

Preparing the ACPI Handoff

The UEFI firmware does not control the PMIC indefinitely; it must hand over runtime power control to the operating system. UEFI drivers prepare this transition by dynamically generating or patching Advanced Configuration and Power Interface (ACPI) tables.

  • OperationRegions: UEFI drivers define ACPI OperationRegion structures in the DSDT (Differentiated System Description Table) or SSDT (Secondary System Description Table). For serial bus PMICs, these are frequently declared using the GenericSerialBus or EmbeddedControl address spaces.
  • AML Methods: The driver populates control methods (such as _ON, _OFF, _PS0, and _PS3) in ACPI Machine Language (AML). When the operating system changes a device's power state, the OS ACPI driver executes the AML bytecode, which issues transactions across the underlying serial bus directly to the power management chip.

Through this coordinated handoff, UEFI drivers establish initial platform stability and guarantee that runtime operating systems have the register definitions necessary to execute modern sleep, wake, and dynamic power policies.