How UEFI PEI Phase Prepares Permanent Memory

The Pre-EFI Initialization (PEI) phase serves as the critical bridge in the UEFI boot flow that transitions a platform from a bare-metal, resource-constrained state to a fully functional environment backed by permanent physical memory. When a computer boots, system RAM is uninitialized and unusable, forcing the system to execute code directly from flash memory and rely on temporary CPU cache storage. The PEI phase systematically detects, trains, tests, and maps the system's dynamic random-access memory (DRAM), builds architectural descriptors for memory allocation, migrates critical runtime data into system RAM, and hands off a fully populated memory map to the Driver Execution Environment (DXE) phase.

Utilizing Temporary Memory via Cache-as-RAM (CAR)

Before permanent memory can be configured, the PEI phase requires a writable memory stack to execute C-based Pre-EFI Initialization Modules (PEIMs). Because main system memory is inaccessible, the Security (SEC) phase configures the CPU's internal L1 or L2 cache as temporary storage using a technique called Cache-as-RAM (CAR).

Under CAR, the CPU's Memory Type Range Registers (MTRRs) are programmed to treat designated cache lines as Write-Back (WB) memory without flushing writes out to the nonexistent system bus. The PEI Foundation initializes its early stack and heap inside this restricted cache space. While CAR provides the necessary environment to run complex C code, it is severely limited in size—often to only a few tens or hundreds of kilobytes—making the initialization of permanent RAM the primary objective of the PEI phase.

Discovery via Serial Presence Detect (SPD)

Permanent memory configuration begins when the PEI Dispatcher loads the platform-specific Memory Initialization PEIM. This module often interfaces with vendor-provided algorithms known as the Memory Reference Code (MRC).

The MRC initiates hardware discovery by querying the Serial Presence Detect (SPD) EEPROMs located on each installed memory module via the System Management Bus (SMBus) or I3C interface. The SPD data provides the memory controller with critical specifications regarding the installed DRAM modules, including:

  • Memory technology and generation (e.g., DDR4, DDR5, LPDDR5)
  • Module density, rank count, and bank architecture
  • Supported clock frequencies, CAS latencies, and base timing constraints (\(t_{RCD}\), \(t_{RP}\), \(t_{RAS}\))
  • Required operational voltages

Memory Training and Controller Configuration

Modern high-speed memory interfaces cannot operate reliably using static timing presets due to microscopic trace-length differences, signal degradation, and temperature variations across motherboard designs. The Memory Initialization PEIM coordinates an extensive hardware calibration sequence known as memory training.

During this stage, the memory controller and the DRAM physical layers (PHY) execute a series of diagnostic and synchronization steps:

  1. ZQ Calibration: Calibrates internal termination resistances to ensure proper signal termination and minimize reflections.
  2. Read/Write Leveling: Adjusts the delay lines for individual clock, strobe (DQS), and data (DQ) signals to compensate for physical PCB trace-length skews.
  3. Vref Centering: Tunes the reference voltage levels to determine the widest, most stable data eye for error-free sampling.
  4. Command/Address Training: Synchronizes the command and address bus timing relative to the system memory clock.

Once training sequences succeed, the memory controller maps the physical address space, interleaves channels for optimal throughput, and clears parity states.

Relocation and the Teardown of Cache-as-RAM

Once physical DRAM is initialized, the PEI phase must transition execution out of temporary cache storage and into main memory:

  1. Memory Range Testing and Allocation: The PEIM tests the lower regions of physical memory to ensure stability and reserves a region to host the permanent PEI stack, heap, and firmware structures.
  2. Data Migration: The PEI Foundation copies the execution stack, global variables, and active state data from CAR into physical memory.
  3. CAR Evacuation and Disabling: The CPU MTRRs are reset to normal caching states. The temporary cache lines are invalidated and disabled, returning the CPU cache to its standard hardware-managed function.
  4. Stack Switching: The CPU stack pointer register (e.g., ESP/RSP) is redirected from the temporary CAR address space to the newly allocated permanent stack address in DRAM.

Creating Hand-Off Blocks (HOBs) for DXE

The final duty of the PEI memory subsystem is documenting the platform's memory map so downstream phases can consume it without re-interrogating hardware. The PEI Foundation creates a series of data structures called Hand-Off Blocks (HOBs).

Specifically, it constructs Resource Descriptor HOBs that define:

  • The total amount and physical address boundaries of detected RAM.
  • Attributes of the memory (e.g., present, initialized, tested, non-volatile).
  • Pre-allocated memory reservations dedicated to firmware runtime usage, ACPI tables, and boot services.

With permanent memory fully operational and documented in the HOB list, the PEI phase concludes by passing the HOB list pointer to the DXE Foundation, allowing UEFI to load high-level device drivers, file systems, and operating system bootloaders into standard system RAM.