How UEFI Communicates With PCI Root Complexes

This article explores the specific protocols utilized by the Unified Extensible Firmware Interface (UEFI) to interface with Peripheral Component Interconnect (PCI) root complexes. It explains the primary mechanism—the PCI Root Bridge I/O Protocol (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL)—and details its core functions, including hardware configuration access, memory-mapped operations, and how it enables firmware to enumerate and manage PCI devices during system boot.

The Primary Protocol: PCI Root Bridge I/O Protocol

In UEFI architecture, the firmware communicates directly with a PCI Root Complex (or Host Bridge) using the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.

A PCI Root Complex serves as the hardware bridge between the CPU/system host bus and the underlying PCI/PCIe bus fabric. Because the hardware registers and access mechanisms of a host bridge vary across chipsets and architectures (such as x86 using ports 0xCF8/0xCFC or memory-mapped ECAM, and ARM utilizing MMIO registers), UEFI abstracts this hardware layer via this protocol.

The protocol is produced by the platform-specific Root Bridge driver (typically part of the Chipset or Silicon DXE phase) and consumed by the generic UEFI PCI Bus Driver (PciBusDxe).

Core Responsibilities of the Protocol

The EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL provides services that allow higher-level firmware components to interact with the PCI hierarchy without knowing the low-level motherboard routing or chipset specifications:

  1. Configuration Space Access (PollMem, PollIo, Mem, Io, Pci.Read, Pci.Write) It provides standardized methods to read from and write to the PCI configuration space (both traditional 256-byte space and extended 4096-byte PCIe space). This allows drivers to query Vendor IDs, Device IDs, and Base Address Registers (BARs).

  2. Address Space Mapping (Mem and Io Services) It translates between CPU system memory/IO space and PCI address domains, ensuring that memory-mapped I/O (MMIO) operations and port I/O accesses reach their targets accurately across different host architectures.

  3. Direct Memory Access (DMA) Operations (Map, Unmap, AllocateBuffer, FreeBuffer) It manages DMA access for PCI devices, ensuring bus master operations follow platform constraints, IOMMU mappings, and cache coherency rules.

How UEFI Uses the Protocol During Enumeration

  1. Root Bridge Publication: The platform-specific chipset driver initializes the host bridge hardware and attaches an instance of EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL to a device handle for each root bridge present.
  2. Bus Scanning: The platform-independent PciBusDxe driver binds to the protocol instance and recursively scans configuration space using the protocol's Pci.Read services to identify bridges, switches, and endpoints.
  3. Resource Allocation: Once devices are enumerated, the PCI bus driver calculates resource requirements (I/O, 32-bit MMIO, 64-bit MMIO) and assigns base addresses via configuration write calls provided by the protocol.
  4. Device Protocol Creation: Finally, the PCI bus driver produces instances of EFI_PCI_IO_PROTOCOL for individual peripheral devices, allowing end-device drivers (such as NVMe, network, or graphics drivers) to communicate with their respective hardware.