Why Sequentially Laminated Buried Vias Increase PCB Costs

Sequentially laminated buried vias significantly drive up the fabrication costs of high-density interconnect (HDI) printed circuit boards (PCBs) primarily due to the need for multiple lamination cycles, repeated drilling and plating processes, and the resulting decline in manufacturing yields. This article provides a comprehensive breakdown of these specific manufacturing challenges, explaining how additional production time, specialized materials, strict registration tolerances, and rigorous inspection requirements directly translate to higher expenses for complex electronics.

Multiple Lamination Cycles

Standard multilayer PCBs are manufactured using a single lamination cycle, where all copper and prepreg layers are pressed together at once. However, when a design incorporates buried vias across different layer pairs, the manufacturer must use sequential lamination.

Each sequence requires building a sub-composite board, laminating it under high heat and pressure, and then repeating the process to add more layers. Because lamination presses run for hours at a time, every additional lamination cycle exponentially increases the machine time, energy consumption, and labor required to finish a single board.

Repeated Drilling and Plating Steps

Buried vias connect internal layers without reaching the outer surfaces, meaning they must be formed before the outer layers are added. In a sequentially laminated HDI board, each sub-assembly must be treated like an individual PCB.

For every lamination sequence, the manufacturer must perform a complete set of fabrication steps:

• Mechanical or laser drilling of the vias.
• Desmearing and cleaning the holes.
• Electroless copper deposition followed by electroplating.
• Imaging and etching the circuit patterns.

Repeating these chemical and mechanical processes multiple times for a single final product drastically increases both material consumption and factory floor bottlenecks.

Tight Registration Tolerances and Material Movement

Every time a PCB undergoes a lamination cycle, the fiberglass and resin materials expand and contract due to intense heat and pressure. In HDI electronics, where trace widths and via pads are microscopic, this material instability makes layer-to-layer alignment—known as registration—extremely difficult.

To combat this, manufacturers must use expensive, high-performance laminate materials with greater dimensional stability. Additionally, they must employ advanced X-ray alignment and optical registration systems to ensure that newly drilled vias align perfectly with the internal pads from previous lamination cycles.

Via Plugging and Planarization Requirements

When buried vias are created in a sub-composite layer, the resulting holes cannot simply be left empty before the next layers are pressed on top. Doing so would cause resin starvation or trapped air pockets (voids) during the next lamination cycle, leading to board failure.

Therefore, these vias must be plugged with specialized conductive or non-conductive epoxy paste. After plugging, the board must be cured and mechanically planarized (sanded down) so the surface is completely flat for the next copper layer. This adds yet another specialized, time-consuming step to the fabrication process.

Decreased Manufacturing Yields and Scrapped Boards

The cumulative effect of multiple processing steps is a higher probability of defects. A single misalignment, plating void, or etching error during the third lamination cycle ruins all the successful work completed in the first two cycles.

Because internal buried vias cannot be reworked or repaired once laminated over, any defect found during intermediate Automated Optical Inspection (AOI) or final electrical testing results in the entire board being scrapped. Manufacturers must factor this lower yield rate into their pricing, passing the cost of the scrapped materials and lost time onto the customer to maintain profitability.