Why Cross-Coupled SR Latches Have an Invalid State

This article explains why cross-coupled Set-Reset (SR) latches enter an invalid and indeterminate state when both inputs are activated simultaneously. It covers the fundamental architecture of NOR and NAND latches, the violation of boolean logic rules concerning complementary outputs, and how race conditions and metastability make the circuit's subsequent state completely unpredictable in digital electronics.

An SR latch is a fundamental bistable multivibrator circuit used to store one bit of information. It is typically constructed by cross-coupling two NOR gates or two NAND gates, meaning the output of each gate is fed back into the input of the other. Under normal operation, the circuit maintains two outputs: \(Q\) (the current state) and \(\overline{Q}\) (the exact inverse, or complement, of \(Q\)).

The "invalid" state occurs immediately when both the Set (S) and Reset (R) inputs are made active at the same time. In a standard cross-coupled NOR latch, an active input is a logic High (1). Knowing that a NOR gate outputs a Low (0) whenever any of its inputs are High (1), setting both S and R to 1 forces the outputs of both gates to 0.

Consequently, both \(Q\) and \(\overline{Q}\) become 0. This is considered logically invalid because the fundamental rule of a latch dictates that \(Q\) and \(\overline{Q}\) must be opposites. The same violation occurs in a cross-coupled NAND latch when both inputs are pulled Low (0, the active state for NAND latches), which forces both \(Q\) and \(\overline{Q}\) to a logic High (1). While the circuit is physically stable while holding these identical outputs, it breaks the logic abstraction required by downstream digital components.

The "indeterminate" state occurs the moment the user tries to exit the invalid state by returning both the S and R inputs to their inactive states simultaneously (0 for a NOR latch, 1 for a NAND latch) to hold the memory. This action triggers a critical timing issue known as a race condition.

When S and R are deactivated at the exact same time, both gates attempt to transition their outputs simultaneously based on the feedback from the other gate. In a purely theoretical simulation with identical gates, the outputs would oscillate back and forth forever. However, in physical electronics, no two logic gates are completely identical due to microscopic variations in manufacturing, temperature, and wire length.

Because of these physical discrepancies, one gate will always have a slightly faster propagation delay than the other. The faster gate will transition first, and its new output will feed back into the slower gate, forcing the slower gate into the opposite state. Because it is impossible for a circuit designer to predict which gate will win this microscopic race, the final stored state of the latch (\(Q=1\) or \(Q=0\)) is completely random and indeterminate.

Furthermore, if the inputs transition within a precise picosecond window, the latch can enter a state called metastability. In a metastable state, the outputs hover at a voltage level somewhere between a valid logic High and a valid logic Low for an unpredictable amount of time before thermal noise eventually pushes the circuit randomly into a 1 or a 0. Because digital systems rely on deterministic, predictable behavior, activating both Set and Reset inputs simultaneously is strictly forbidden in SR latch design.