Understanding SPI Modes: Clock Polarity and Phase

This article provides a comprehensive guide to the four operating modes of the Serial Peripheral Interface (SPI) protocol. It explains how the combinations of Clock Polarity (CPOL) and Clock Phase (CPHA) define data transmission timing between a master and a peripheral device, breaking down the exact behavior of SPI Modes 0, 1, 2, and 3.

In Serial Peripheral Interface (SPI) electronics, synchronous communication relies on a shared clock signal generated by the controller (master) device. To ensure data is read and written at the exact right microsecond, both the controller and the peripheral (slave) device must agree on the timing configuration. This configuration is defined by two parameters: Clock Polarity (CPOL) and Clock Phase (CPHA).

Clock Polarity (CPOL)

Clock Polarity determines the idle state of the clock signal (SCLK) when no data is being transferred. The idle state is the voltage level of the clock line before the transmission begins and after it ends.

  • CPOL = 0: The clock signal idles at a logic low level (0V). The active state of the clock is high. The leading edge is a rising edge (low-to-high transition), and the trailing edge is a falling edge (high-to-low transition).
  • CPOL = 1: The clock signal idles at a logic high level (typically 3.3V or 5V). The active state of the clock is low. The leading edge is a falling edge (high-to-low transition), and the trailing edge is a rising edge (low-to-high transition).

Clock Phase (CPHA)

Clock Phase determines which edge of the clock signal is used to sample (read) the data and which edge is used to shift (change/write) the data.

  • CPHA = 0: Data is sampled on the leading (first) edge of the clock cycle. Data is shifted out on the trailing (second) edge of the clock cycle. Because data is read on the very first clock transition, the data must be stable on the line before the first clock edge occurs.
  • CPHA = 1: Data is shifted out on the leading (first) edge of the clock cycle. Data is sampled on the trailing (second) edge of the clock cycle.

The Four SPI Combinations (SPI Modes)

Combining the two states of CPOL and the two states of CPHA results in four distinct timing configurations, universally referred to as SPI Modes 0, 1, 2, and 3.

SPI Mode 0 (CPOL = 0, CPHA = 0)

Mode 0 is the most common implementation of SPI.

  • Idle State: Low (0).
  • Data Sampling (Read): Occurs on the leading, rising edge (transition from low to high).
  • Data Shifting (Write): Occurs on the trailing, falling edge (transition from high to low).

SPI Mode 1 (CPOL = 0, CPHA = 1)

  • Idle State: Low (0).
  • Data Shifting (Write): Occurs on the leading, rising edge (transition from low to high).
  • Data Sampling (Read): Occurs on the trailing, falling edge (transition from high to low).

SPI Mode 2 (CPOL = 1, CPHA = 0)

  • Idle State: High (1).
  • Data Sampling (Read): Occurs on the leading, falling edge (transition from high to low).
  • Data Shifting (Write): Occurs on the trailing, rising edge (transition from low to high).

SPI Mode 3 (CPOL = 1, CPHA = 1)

  • Idle State: High (1).
  • Data Shifting (Write): Occurs on the leading, falling edge (transition from high to low).
  • Data Sampling (Read): Occurs on the trailing, rising edge (transition from low to high).

Implementing SPI Modes in Hardware

Peripheral devices, such as sensors and memory chips, usually have a fixed SPI mode hardcoded into their silicon by the manufacturer. Microcontrollers, which act as the SPI master, have configurable registers that allow the programmer to change the CPOL and CPHA bits. To establish successful communication, the engineer must read the peripheral's datasheet, identify the required CPOL and CPHA combination, and configure the microcontroller's SPI registers to match that exact mode.