How Sense Amplifiers Restore Charge in DRAM Refresh Cycles

Dynamic Random-Access Memory (DRAM) stores digital information as electrical charges within microscopic single-capacitor cells, which naturally leak energy over milliseconds. To prevent catastrophic data corruption, memory subsystems execute periodic refresh cycles relying heavily on specialized components called sense amplifiers. This article provides a comprehensive overview of the physical and electrical processes sense amplifiers use to detect degraded voltage levels, amplify the signals, and restore the leaked charge back into the DRAM cells during a refresh operation.

The Architecture of a Single-Capacitor DRAM Cell

A standard DRAM cell consists of one metal-oxide-semiconductor field-effect transistor (MOSFET) and one storage capacitor, an arrangement commonly referred to as a 1T1C cell. The capacitor holds electrons to represent a binary "1" (charged to the supply voltage, \(V_{DD}\)) or lacks electrons to represent a binary "0" (0 volts). The transistor acts as an access switch controlled by a horizontal wire called the wordline, while a vertical wire called the bitline transfers data into and out of the cell. Because the capacitor is microscopic, its capacitance is measured in femtofarads, and subthreshold leakage currents through the transistor cause the stored charge to dissipate rapidly.

Step 1: Bitline Precharging

Before a refresh cycle can read and restore the charge of a DRAM cell, the sense amplifier prepares the bitlines. Sense amplifiers operate using differential signaling, meaning each amplifier is connected to a pair of bitlines: a true bitline (connected to the target cell) and a complementary reference bitline.

The precharge circuit equalizes both bitlines to an exact intermediate voltage, which is half of the supply voltage (\(V_{DD}/2\)). Once both bitlines are stabilized at \(V_{DD}/2\), the precharge circuit is disconnected, leaving the bitlines electrically floating at this reference voltage.

Step 2: Charge Sharing and Destructive Read

To initiate the refresh of a specific row of cells, the memory controller activates the corresponding wordline. This turns on the access transistors for every cell in that row, physically connecting the storage capacitors to their respective bitlines.

Because the bitline has a much larger capacitance than the tiny storage capacitor, the remaining charge in the cell shares with the bitline, causing only a minuscule shift in the bitline's voltage:

  • If the cell originally held a degraded "1" (a voltage slightly above \(V_{DD}/2\)), the bitline voltage increases by a few dozen millivolts (\(V_{DD}/2 + \Delta V\)).
  • If the cell held a degraded "0" (a voltage slightly below \(V_{DD}/2\)), the bitline voltage decreases slightly (\(V_{DD}/2 - \Delta V\)).

This process is known as a destructive read because the capacitor's remaining charge is completely depleted onto the bitline to create this tiny voltage differential.

Step 3: Differential Sensing and Amplification

At its core, a sense amplifier is a pair of cross-coupled CMOS inverters that form a bistable latch. While the charge sharing occurs, the sense amplifier remains inactive. Once the tiny voltage difference (\(\Delta V\)) is established between the target bitline and the reference bitline (which remains at \(V_{DD}/2\)), the sense amplifier is triggered.

Power is applied to the sense amplifier via two activation lines: a pull-up line (connected to \(V_{DD}\)) and a pull-down line (connected to ground). Because of the positive feedback loop created by the cross-coupled inverters, the amplifier detects the slight imbalance between the two bitlines:

  • The bitline with the slightly higher voltage causes the opposing inverter to pull the lower-voltage bitline all the way down to 0V.
  • Simultaneously, the inverter connected to the lower-voltage bitline drives the higher-voltage bitline all the way up to the full \(V_{DD}\) supply voltage.

Step 4: Charge Restoration

As the sense amplifier latches and drives the active bitline to either the full \(V_{DD}\) (for a "1") or 0V (for a "0"), the wordline remains active. Because the access transistor is still open, the full voltage now present on the bitline flows directly back into the cell's storage capacitor.

The capacitor is fully recharged to its pristine state, effectively overwriting the leaked charge level with a fully restored signal. Finally, the wordline is deactivated to turn off the access transistor, trapping the fresh charge inside the capacitor. The sense amplifier is then turned off, and the bitlines are precharged back to \(V_{DD}/2\) in preparation for the next memory access or refresh cycle.