How SAR ADCs Use Binary Search to Digitize Voltages

Successive-Approximation Register Analog-to-Digital Converters (SAR ADCs) are widely used in modern electronics to translate continuous analog voltage signals into discrete digital numbers. This article explains how a SAR ADC utilizes a binary search algorithm to efficiently determine the digital value of an input voltage by systematically halving the possible voltage range and comparing it against an internal reference.

Core Components of a SAR ADC

To execute a binary search, a SAR ADC relies on four primary internal components working in a feedback loop:

  • Sample-and-Hold Circuit (S/H): Captures the incoming analog voltage (\(V_{IN}\)) and keeps it steady during the conversion process.
  • Digital-to-Analog Converter (DAC): Converts the current digital guess from the register into an analog voltage (\(V_{DAC}\)) using a known reference voltage (\(V_{REF}\)).
  • Comparator: Compares the held input voltage (\(V_{IN}\)) with the generated DAC voltage (\(V_{DAC}\)) and outputs a logic high or low.
  • Successive-Approximation Register (SAR): The digital logic unit that executes the binary search algorithm based on the comparator's output.

The Binary Search Algorithm Step-by-Step

The binary search process determines the digital output one bit at a time, starting from the Most Significant Bit (MSB) and moving down to the Least Significant Bit (LSB).

  1. Sampling: The Sample-and-Hold circuit captures the analog input voltage (\(V_{IN}\)). The SAR resets all its bits to 0.
  2. Testing the MSB: The SAR sets the Most Significant Bit (MSB) to 1, leaving all other bits at 0. For an \(N\)-bit ADC, this represents half of the full-scale reference voltage (\(\frac{1}{2} V_{REF}\)).
  3. First Comparison: The internal DAC outputs \(\frac{1}{2} V_{REF}\). The comparator checks if \(V_{IN}\) is greater than or less than \(V_{DAC}\).
    • If \(V_{IN} > V_{DAC}\), the comparator outputs a 1, and the SAR keeps the MSB set to 1.
    • If \(V_{IN} < V_{DAC}\), the comparator outputs a 0, and the SAR resets the MSB back to 0.
  4. Moving to the Next Bit: The SAR moves to the next bit down and sets it to 1. Depending on the result of the first step, the DAC now outputs either \(\frac{3}{4} V_{REF}\) (if the MSB remained 1) or \(\frac{1}{4} V_{REF}\) (if the MSB was reset to 0).
  5. Repeating the Process: The comparator evaluates the new \(V_{DAC}\) against \(V_{IN}\) and keeps or resets the second bit accordingly. This process of halving the remaining voltage range continues until the Least Significant Bit (LSB) is tested.
  6. Output: Once the LSB is determined, the binary search is complete. The digital word stored in the SAR is output as the final digital representation of the input voltage.

Concrete Example: A 4-Bit SAR ADC

Assume a 4-bit SAR ADC has a reference voltage (\(V_{REF}\)) of 16V and receives an analog input voltage (\(V_{IN}\)) of 11.2V.

  • Cycle 1 (Bit 3 - MSB): The SAR guesses 1000, which sets \(V_{DAC}\) to 8V (\(\frac{1}{2}\) of 16V). Since 11.2V > 8V, the MSB remains 1.
  • Cycle 2 (Bit 2): The SAR sets the next bit, guessing 1100. This sets \(V_{DAC}\) to 12V (\(8V + 4V\)). Since 11.2V < 12V, this bit is too high and is reset to 0. The register now holds 1000.
  • Cycle 3 (Bit 1): The SAR sets the third bit, guessing 1010. This sets \(V_{DAC}\) to 10V (\(8V + 2V\)). Since 11.2V > 10V, this bit remains 1.
  • Cycle 4 (Bit 0 - LSB): The SAR sets the final bit, guessing 1011. This sets \(V_{DAC}\) to 11V (\(8V + 2V + 1V\)). Since 11.2V > 11V, the LSB remains 1.

The conversion finishes in 4 clock cycles. The final digital output is 1011 (which represents 11V, the closest digital approximation to 11.2V for this resolution).

Why the Binary Search Approach is Effective

By using a binary search algorithm, an \(N\)-bit SAR ADC only requires \(N\) clock cycles to complete a conversion. In contrast, a linear search (such as in a ramp-compare ADC) would require up to \(2^N\) clock cycles. For a 16-bit ADC, a SAR architecture takes 16 cycles to find the voltage, whereas a linear search could take up to 65,536 cycles. This makes SAR ADCs an ideal balance of speed, resolution, and low power consumption for data acquisition systems.