How RHBD Logic Cells Survive Space Radiation

Space electronics face constant bombardment from cosmic rays and solar particles, which cause severe degradation and random errors in standard microchips. To survive these harsh environments without relying on specialized, expensive manufacturing foundries, engineers use Radiation-Hardened-by-Design (RHBD) techniques. This article provides a comprehensive overview of how RHBD logic cells utilize Enclosed Layout Transistors (ELTs) to physically prevent leakage currents caused by Total Ionizing Dose (TID), while simultaneously deploying Triple Modular Redundancy (TMR) at the circuit level to mask transient data corruption.

Understanding the Threat: Total Ionizing Dose (TID)

Total Ionizing Dose (TID) is the cumulative damage inflicted on semiconductor materials by ionizing radiation over time. When high-energy photons or protons pass through a silicon dioxide insulator, they generate electron-hole pairs.

Because electrons are highly mobile, they are quickly swept out of the oxide. However, the positively charged holes move much slower and become trapped in the silicon dioxide, particularly in the thicker Shallow Trench Isolation (STI) oxide regions that separate standard transistors. Over time, this buildup of positive charge creates an unwanted electric field. In N-channel MOS (NMOS) transistors, this trapped charge attracts electrons to the edges of the transistor channel, forming a permanent, parasitic conductive path between the source and drain. The transistor can no longer be turned off completely, leading to massive leakage currents, logic failure, and eventual system burnout.

Enclosed Layout Transistors (ELTs)

To combat TID-induced leakage using standard commercial CMOS processes, engineers alter the physical geometry of the transistor by using Enclosed Layout Transistors (ELTs).

In a standard transistor layout, the drain and source sit on opposite sides of a straight gate, and the edges of this channel touch the vulnerable STI field oxide. An ELT completely eliminates these exposed edges. In an ELT configuration:

  • Concentric Geometry: The drain (or source) is placed at the very center of the layout.
  • Closed-Loop Gate: The polysilicon gate is drawn as a continuous, closed ring—often circular, octagonal, or rectangular with rounded corners—completely surrounding the central terminal.
  • Outer Terminal: The remaining terminal (source or drain) surrounds the outside of the gate ring.

Because the gate forms an unbroken loop separating the source and the drain, there is no region where the active channel between the source and drain touches the thick STI oxide. Without a shared border along the field oxide, the trapped positive charges from TID cannot form a parasitic leakage path between the source and drain. Guard rings—heavily doped regions of silicon—are also placed around the exterior of the ELT to absorb any stray charge carriers and prevent leakage between adjacent transistors.

Triple Modular Redundancy (TMR)

While ELTs successfully protect the physical hardware from the slow, cumulative degradation of TID, space radiation also causes Single Event Effects (SEEs). When a single heavy ion strikes a sensitive node within a logic cell, it injects a burst of charge that can instantly flip a stored bit (a Single Event Upset) or create a momentary voltage spike (a Single Event Transient). ELTs cannot stop these instantaneous logic errors, which is why RHBD logic cells incorporate Triple Modular Redundancy (TMR).

TMR is a fault-tolerant architectural technique applied to digital logic, particularly memory elements like flip-flops and latches. The process works through simple replication and voting:

  1. Triplication: A single logic cell or flip-flop is replaced by three identical, physically separated copies. All three cells receive the exact same input data and clock signals simultaneously.
  2. Majority Voting: The outputs of all three logic cells are fed into a majority voter circuit. The voter compares the three signals and outputs the state held by at least two of the cells.
  3. Error Masking: If a radiation strike flips the state of one flip-flop, the other two remain unaffected. The voter receives two correct signals and one corrupted signal. It ignores the corrupted minority signal and passes the correct majority value down the logic chain, masking the error in real-time without interrupting system operations.

The Synergy of ELT and TMR in RHBD

True radiation hardness in space electronics requires combining both physical layout modifications and architectural redundancy. If a circuit only uses TMR built with standard straight-gate transistors, the cumulative TID will eventually cause all three redundant branches to suffer from severe leakage currents, draining the spacecraft's power supply and causing total chip failure. Conversely, if a circuit only uses ELTs without TMR, the chip will survive the long-term ionizing dose, but its data will be constantly corrupted by single-event particle strikes.

By building the triplicate logic cells and the majority voter circuits out of Enclosed Layout Transistors, RHBD logic cells achieve comprehensive protection. The ELTs ensure the physical transistors remain functional and leak-free over years of accumulating radiation, while the TMR architecture ensures the data flowing through those transistors remains accurate second by second.