How PMOS Pass Elements Enable Low-Dropout Voltage Regulation

This article explores how a P-channel Metal-Oxide-Semiconductor (PMOS) transistor functions as the primary pass element in low-dropout (LDO) voltage regulators, enabling them to maintain a stable output even when the input and output voltages are nearly identical. We will examine the fundamental differences between PMOS and traditional NPN or NMOS architectures, focusing on gate drive requirements, on-resistance characteristics, and how pulling the gate voltage toward ground allows the PMOS to operate efficiently with minimal voltage headroom.

The Challenge of Dropout Voltage

In linear voltage regulators, the pass element acts as a variable resistor placed between the input voltage (\(V_{IN}\)) and the output voltage (\(V_{OUT}\)). The "dropout voltage" is the minimum difference between \(V_{IN}\) and \(V_{OUT}\) required for the regulator to maintain its specified output voltage.

Traditional linear regulators use NPN bipolar junction transistors or NMOS transistors in a voltage-follower configuration. These components require a control voltage at the base or gate that is significantly higher than the output voltage to turn on fully. When \(V_{IN}\) drops close to \(V_{OUT}\), there is no longer enough voltage available to drive the transistor, causing the regulator to fall out of regulation. Typical NPN regulators require a headroom of 1.5V to 2V, making them inefficient for low-voltage or battery-powered electronics.

How the PMOS Pass Element Solves the Headroom Problem

A PMOS pass element operates differently because of how it is oriented and driven within the LDO circuit. In a PMOS LDO, the source terminal is connected to \(V_{IN}\), and the drain terminal is connected to \(V_{OUT}\).

To turn a PMOS transistor on, its gate voltage (\(V_G\)) must be pulled lower than its source voltage (\(V_{IN}\)) by at least the transistor's threshold voltage (\(V_{TH}\)). Because the error amplifier inside the LDO can pull the gate all the way down to ground (0V), the PMOS does not require any voltage above \(V_{IN}\) to activate.

When \(V_{IN}\) and \(V_{OUT}\) are nearly equal, the error amplifier detects that the output voltage is starting to droop. In response, it pulls the PMOS gate closer to ground. This increases the gate-to-source voltage differential (\(V_{GS}\)), turning the PMOS transistor on harder and allowing it to pass current without needing extra voltage headroom at the input.

Operating in the Linear (Ohmic) Region

As \(V_{IN}\) approaches \(V_{OUT}\), the drain-to-source voltage across the PMOS becomes very small. Under these conditions, the PMOS transistor transitions from the saturation region into the linear (or ohmic) region of operation.

In the linear region, the PMOS acts purely like a low-value resistor. The minimum voltage difference required to maintain regulation is determined strictly by Ohm's Law:

\[V_{DROPOUT} = I_{LOAD} \times R_{DS(on)}\]

Where \(I_{LOAD}\) is the current demanded by the load, and \(R_{DS(on)}\) is the drain-to-source on-resistance of the PMOS transistor. Because modern PMOS transistors are engineered to have an extremely low \(R_{DS(on)}\)—often just a few milliohms—the resulting dropout voltage can be less than 100 millivolts. As long as \(V_{IN}\) remains above \(V_{OUT}\) plus this tiny resistive drop, the LDO will maintain strict regulation.

Voltage-Driven Efficiency

Another reason the PMOS maintains regulation effectively at low headroom is that it is a voltage-driven device rather than a current-driven device (like PNP transistors, which are also used in some LDOs).

When a PNP pass element approaches dropout, it requires a massive surge in base current to stay on, which gets wasted to ground and drains the power supply. A PMOS gate, however, is capacitive and requires almost zero steady-state current to remain open. Therefore, when input and output voltages are nearly equal, the PMOS can be driven fully on by the error amplifier without wasting power, ensuring maximum efficiency right up to the physical limits of its internal resistance.