How IEEE 1149.1 Boundary Scan Tests BGA Pin Connectivity

This article explains how IEEE 1149.1 boundary scan testing, commonly known as JTAG, verifies pin-to-pin connectivity between Ball Grid Array (BGA) devices when physical test points are impossible to access. By utilizing internal shift registers built directly into the silicon of compliant integrated circuits, boundary scan replaces traditional physical probing with digital test vectors. You will learn the architecture of boundary scan cells, the role of the Test Access Port (TAP), the mechanics of the EXTEST instruction, and how this methodology detects open and short circuits hidden beneath densely packed BGA packages.

The Challenge of BGA Packaging

Ball Grid Array (BGA) packages mount directly to a printed circuit board (PCB) using a grid of solder balls located entirely underneath the component body. High-density PCB designs often route traces from these solder balls directly into inner board layers using micro-vias. Because the pins are hidden beneath the package and the traces are buried within the board, traditional In-Circuit Testing (ICT) using physical "bed-of-nails" fixtures cannot probe the connections to check for manufacturing defects. IEEE 1149.1 boundary scan resolves this by moving the test points inside the chips themselves.

Boundary Scan Architecture

To understand how connectivity is verified without physical probes, it is necessary to understand the hardware embedded inside an IEEE 1149.1-compliant BGA device.

  • Boundary Scan Cells: Every digital input and output pin on a compliant BGA is connected to a dedicated boundary scan cell located between the physical pin and the chip's internal core logic. During normal operation, these cells are invisible, allowing signals to pass freely. During testing, these cells intercept the signals, allowing the test system to manually drive a signal out of a pin or read the state of a signal coming into a pin.
  • Boundary Scan Register (BSR): All the individual boundary scan cells inside a chip are linked together sequentially to form one continuous shift register around the perimeter (boundary) of the silicon die.
  • Test Access Port (TAP): The BSR is controlled via a four- or five-pin interface known as the TAP. The pins include Test Clock (TCK), Test Mode Select (TMS), Test Data In (TDI), Test Data Out (TDO), and an optional Test Reset (TRST).
  • The Scan Chain: On a PCB with multiple BGA devices, the TDO pin of the first BGA is wired to the TDI pin of the next BGA. This creates a continuous serial data path, or "scan chain," that links the boundary scan registers of multiple chips together, accessible through a single connector on the edge of the board.

How Pin-to-Pin Connectivity is Verified

To test the physical copper traces connecting one BGA pin to another, the boundary scan controller executes a specific IEEE 1149.1 instruction called EXTEST (External Test). The EXTEST mode isolates the internal core logic of the BGAs and gives the boundary scan cells complete control over the physical pins.

The verification process follows a strictfour-step cycle:

  1. Load (Shift-DR): The test controller shifts a specific serial pattern of 1s and 0s (a test vector) into the TDI pin. This data travels through the scan chain until the targeted output boundary scan cell on "BGA 1" holds a specific logic value.
  2. Drive (Update-DR): The TAP controller issues an update command. The boundary scan cell on BGA 1 drives its stored logic value out onto the physical BGA solder ball and across the PCB trace.
  3. Sample (Capture-DR): Almost simultaneously, the boundary scan cell connected to the receiving solder ball on "BGA 2" captures the logic level present on its pin.
  4. Read (Shift-DR): The captured data in BGA 2 is shifted out of the chain via the TDO pin back to the test software, while the next test vector is simultaneously shifted in through the TDI pin.

Detecting Manufacturing Faults

By comparing the data shifted into the transmitting BGA pins with the data captured by the receiving BGA pins, the boundary scan software can pinpoint physical manufacturing defects without touching the board.

  • Pass Condition: If BGA 1 drives a logic 1 and BGA 2 captures a logic 1 (and the same holds true for a logic 0), the solder joints on both BGAs and the PCB trace connecting them are intact.
  • Open Circuits: If a solder ball under BGA 1 or BGA 2 is cracked or missing, the signal will not cross the gap. When BGA 1 toggles between driving a 1 and a 0, the receiving cell on BGA 2 will fail to see the change, typically reading a constant float value (stuck-at fault).
  • Short Circuits (Bridging): To find shorts between adjacent solder balls, the software drives opposite logic values on neighboring pins. For example, Pin A drives a 1 while adjacent Pin B drives a 0. If solder has bridged the two balls underneath the BGA, the two signals will clash. The receiving pins at the other end of the traces will read corrupted logic levels, alerting the test software that a short circuit exists between those two specific nets.

The Role of BSDL Files

The test software knows which bit in the long serial chain corresponds to which physical BGA ball by reading a Boundary Scan Description Language (BSDL) file. Provided by the chip manufacturer, the BSDL file maps the exact order of the boundary scan cells to the physical pinout of the BGA. By combining the BSDL files of the chips with the PCB's CAD netlist, automated test software can automatically generate the exact test vectors needed to verify 100% of the digital interconnects between inaccessible BGA pins.