How Floating-Gate and Charge-Trap NAND Flash Store Multi-Bits

This article provides a technical breakdown of how modern high-density NAND flash memory stores multiple bits of data within a single memory cell. It explores the physics of quantum tunneling, the architectural differences between floating-gate and charge-trap transistors, and the precise voltage manipulation required to achieve Multi-Level Cell (MLC), Triple-Level Cell (TLC), and Quad-Level Cell (QLC) storage densities.

The Physics of Flash Memory Cells

At the core of NAND flash memory is a specialized type of Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). Standard transistors act as simple switches, representing a single bit of data: on (1) or off (0). Flash memory transistors modify this design by introducing a mechanism to trap electrons between the control gate and the underlying silicon channel.

The presence or absence of these trapped electrons alters the transistor’s threshold voltage (\(V_{th}\))—the specific voltage required to turn the transistor on and allow current to pass through the channel. By precisely controlling the amount of charge stored, engineers can create multiple distinct threshold voltage levels within a single transistor, allowing it to represent more than just a single 1 or 0.

Floating-Gate Transistors

Floating-gate (FG) technology was the industry standard for planar (2D) NAND flash for decades. A floating-gate transistor features two gates: a control gate on top and a conductive polysilicon "floating" gate beneath it. The floating gate is completely surrounded by an insulating oxide layer, electrically isolating it from the rest of the transistor.

To write (program) data, a high positive voltage is applied to the control gate. This pulls electrons from the silicon substrate through the thin tunnel oxide layer via a quantum mechanical process known as Fowler-Nordheim tunneling. Once inside the floating gate, the electrons are trapped. Because the floating gate is an electrical conductor, the charge distributes evenly throughout the material. To erase the cell, a high voltage is applied in reverse (to the substrate), pushing the electrons back out of the floating gate.

Charge-Trap Transistors

As memory manufacturers transitioned from 2D planar NAND to 3D NAND to increase storage density, floating-gate transistors became too large and suffered from cell-to-cell interference. Charge-trap (CT) technology solved this problem.

Instead of a conductive polysilicon floating gate, a charge-trap transistor uses an insulating layer—typically made of silicon nitride—to store electrons. Because silicon nitride is an insulator, electrons do not flow freely through it. Instead, they become physically localized in microscopic "traps" within the material's atomic structure.

This localization offers two major advantages for high-density multi-bit storage:

  1. Reduced Interference: Because the charge is immobilized, it generates less electrostatic interference with adjacent memory cells, allowing cells to be packed closer together.
  2. Higher Reliability: If a defect occurs in the surrounding oxide layer, a floating gate will leak all of its conductive charge, corrupting the data. A charge-trap layer will only lose the electrons immediately adjacent to the defect, preserving the integrity of the multi-bit state.

Storing Multiple Bits: Voltage Threshold States

Storing multiple bits in a single cell—whether using a floating gate or a charge trap—relies on dividing a transistor's total voltage window into smaller, discrete voltage distributions. The number of states required is equal to \(2^n\), where \(n\) is the number of bits per cell.

  • Single-Level Cell (SLC): Stores 1 bit. It requires \(2^1 = 2\) voltage states (representing 0 or 1).
  • Multi-Level Cell (MLC): Stores 2 bits. It requires \(2^2 = 4\) distinct voltage states (representing 00, 01, 10, or 11).
  • Triple-Level Cell (TLC): Stores 3 bits. It requires \(2^3 = 8\) distinct voltage states (representing 000 through 111).
  • Quad-Level Cell (QLC): Stores 4 bits. It requires \(2^4 = 16\) distinct voltage states (representing 0000 through 1111).

In a QLC transistor, the memory controller must be able to inject and detect 16 precise, non-overlapping quantities of electrons within that single microscopic cell.

Programming Precision: Incremental Step Pulse Programming (ISPP)

Injecting an exact number of electrons into a floating gate or charge trap to hit one of 8 (TLC) or 16 (QLC) narrow voltage windows cannot be done with a single blast of electricity. Doing so would overshoot the target threshold voltage.

Instead, NAND flash controllers use a method called Incremental Step Pulse Programming (ISPP). The controller applies a very short programming voltage pulse to the control gate, moving a small batch of electrons into the trap layer. Immediately following the pulse, the controller performs a "verify" operation—applying a reference voltage to see if the cell has reached the desired threshold voltage.

If the threshold voltage is still too low, the controller applies another programming pulse at a slightly higher voltage, followed by another verification check. This step-and-verify loop repeats until the exact amount of charge is trapped, placing the cell precisely within the target voltage window for the desired multi-bit value.

Reading Multi-Bit Cells

Reading data from a multi-bit cell is a process of elimination using variable reference voltages. Because trapped electrons repel the positive voltage applied to the control gate, a cell with a large number of trapped electrons requires a higher voltage to turn on and conduct current through its channel.

To read a TLC cell (8 states), the memory controller applies a series of predetermined read reference voltages to the control gate, positioned in the narrow gaps between the 8 target voltage distributions. By sensing whether the transistor conducts current or remains off at each reference point, the controller narrows down the exact threshold voltage of the cell, translating that analog voltage level back into a 3-bit digital binary sequence.