How Digital Multiplexers Route Multiple Inputs to One Output

A digital multiplexer, commonly known as a MUX, is a fundamental electronic component that selects one of several input data streams and forwards it to a single output line. This article provides a comprehensive breakdown of how multiplexers achieve this data routing using internal logic gates, binary select lines, and address decoding. By understanding the relationship between data inputs, control signals, and Boolean logic, you will learn the exact mechanism behind how routing electronics manage and consolidate multiple digital signals efficiently.

The Core Components of a Multiplexer

To understand how a multiplexer routes data, you must first understand its three primary interfaces:

  • Data Inputs (\(D\)): The multiple lines carrying incoming digital signals (streams of 1s and 0s). The number of inputs is usually a power of two (2, 4, 8, 16, etc.).
  • Select Lines (\(S\)): The control pins used to choose which data input is allowed to pass through.
  • Output Line (\(Y\)): The single pathway out of the multiplexer that carries the selected input data stream.

A mathematical rule governs the relationship between the inputs and the select lines: \(2^n = N\), where \(n\) is the number of select lines and \(N\) is the number of data inputs. For example, a 4-to-1 multiplexer has 4 data inputs and requires 2 select lines (\(2^2 = 4\)). An 8-to-1 multiplexer requires 3 select lines (\(2^3 = 8\)).

The Routing Mechanism: Logic Gates in Action

Inside the multiplexer, routing is not done by moving physical switches. Instead, it is achieved through a network of digital logic gates—specifically NOT gates (inverters), AND gates, and a final OR gate.

1. Address Decoding with Select Lines

The routing process begins at the select lines. A binary code is applied to these lines by an external controller, such as a microprocessor. Using NOT gates, the multiplexer generates both the original select signals and their inverted opposites. This creates a unique internal binary "address" for every possible combination of select line states.

2. Gating the Inputs with AND Gates

Every individual data input line is connected to its own dedicated AND gate. Along with the data input, each AND gate also receives a specific combination of the select line signals.

An AND gate only outputs a "1" (High) if all of its inputs are "1". The multiplexer is wired so that for any given binary code on the select lines, only one AND gate receives all "1s" from the select logic.

  • Unselected Gates: All other AND gates receive at least one "0" from the select lines. Because of this, these gates are effectively "closed" or disabled. Whatever data is streaming into them is blocked, and their output remains a constant "0".
  • The Selected Gate: The single AND gate that receives all "1s" from the select lines is "opened" or enabled. Now, its output depends entirely on its data input stream. If the data stream is "1", the gate outputs "1". If the data stream is "0", the gate outputs "0".

3. Combining into One Output with an OR Gate

The outputs of all the internal AND gates feed into a single, multi-input OR gate. An OR gate outputs a "1" if any of its inputs are "1", and a "0" only if all inputs are "0".

Since all the unselected AND gates are outputting a constant "0", they have no effect on the OR gate. The OR gate simply reacts to the single enabled AND gate. Consequently, the exact data stream from the chosen input passes through the enabled AND gate, through the OR gate, and out the single output line.

Step-by-Step Example: A 4-to-1 Multiplexer

To see this clearly, consider a 4-to-1 MUX with inputs \(D_0, D_1, D_2, D_3\), select lines \(S_1, S_0\), and output \(Y\).

Suppose you want to route the data stream on \(D_2\) to the output \(Y\):

  1. Apply the Select Code: The binary representation for the number 2 is 10. You apply a High signal (1) to \(S_1\) and a Low signal (0) to \(S_0\).
  2. Internal Inversion: Inside the MUX, a NOT gate inverts the \(S_0\) signal from a 0 to a 1.
  3. Enabling the Target Gate: The AND gate connected to \(D_2\) is specifically wired to receive \(S_1\) (which is 1) and the inverted \(S_0\) (which is now 1). Because both control inputs are 1, the \(D_2\) AND gate is unlocked.
  4. Blocking Other Gates: The AND gates for \(D_0\), \(D_1\), and \(D_3\) receive at least one 0 from the 10 select combination. Their outputs are forced to 0.
  5. Final Output: As the data stream on \(D_2\) fluctuates between 1 and 0, the unlocked AND gate mirrors this exact pattern. The final OR gate reads the 0s from the blocked gates and the active stream from the \(D_2\) gate, routing the \(D_2\) stream directly to output \(Y\).

Time-Division Multiplexing (TDM)

In practical routing electronics, multiplexers rarely stay locked on a single input. By rapidly cycling through the binary codes on the select lines using a high-speed clock, a multiplexer can sample small pieces of data from each input in a continuous loop. This technique, known as Time-Division Multiplexing, allows multiple devices to share a single communication medium—such as a single copper wire or fiber-optic cable—by taking turns transmitting their data streams in fractions of a second.