How Current Mirrors Copy and Scale Bias Currents in ICs

This article explores how matched-transistor current mirrors copy and scale bias currents across monolithic integrated circuits (ICs). By leveraging the identical physical properties of transistors fabricated on the same silicon die, engineers can generate a single precise reference current and replicate or scale it across hundreds of internal amplifier stages. The following sections break down the fundamental physics of current mirroring, the geometric techniques used for current scaling, the advantages of monolithic integration, and the circuit topologies used to overcome real-world non-idealities.

The Fundamental Principle of Current Mirroring

A current mirror is a circuit block designed to copy a current flowing through one active device by controlling the current in another active device, keeping the output current constant regardless of loading.

In a basic two-transistor current mirror—whether using Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) or Bipolar Junction Transistors (BJTs)—the governing principle relies on the relationship between control voltage and output current:

  • In MOSFETs: The drain current (\(I_D\)) is controlled by the gate-to-source voltage (\(V_{GS}\)).
  • In BJTs: The collector current (\(I_C\)) is controlled by the base-to-emitter voltage (\(V_{BE}\)).

To copy a current, a reference current (\(I_{REF}\)) is forced into a "diode-connected" input transistor (where the gate is tied to the drain, or the base is tied to the collector). This configuration forces the transistor to automatically generate the exact \(V_{GS}\) or \(V_{BE}\) required to sustain that specific reference current.

Because the gate (or base) and source (or emitter) terminals of the second transistor are wired directly in parallel with the first transistor, both devices share the exact same control voltage. If the two transistors are physically identical and operating at the same temperature, the second transistor will naturally produce an output current (\(I_{OUT}\)) equal to \(I_{REF}\).

Why Monolithic Integration is Critical

Attempting to build a precise current mirror using discrete, off-the-shelf transistors usually yields poor results. Discrete components come from different silicon wafers and manufacturing batches, resulting in slight variations in threshold voltages, oxide thicknesses, and doping profiles. Furthermore, discrete transistors experience different local temperatures during operation, which drastically alters their current-voltage characteristics.

Monolithic integrated circuits solve this problem. Because all components on an IC are fabricated simultaneously on the same microscopic piece of silicon using photolithography, adjacent transistors share nearly identical material properties.

Additionally, placing the transistors side-by-side ensures tight thermal coupling. As the chip heats up during operation, both the reference and output transistors experience the exact same temperature shifts, allowing their electrical parameters to drift together and preserving the accuracy of the current ratio.

Scaling Bias Currents Geometrically

Integrated circuits rarely require the exact same bias current for every stage. High-speed output stages may need milliamps of current, while low-power input stages may only require microamps. Rather than generating multiple independent reference currents, designers use a single reference and scale the output currents geometrically.

Scaling in MOSFETs

The drain current of a MOSFET in saturation is directly proportional to its aspect ratio—the width of its channel (\(W\)) divided by its length (\(L\)). If the channel lengths of the reference transistor (\(M_1\)) and output transistor (\(M_2\)) are kept equal, the current scales purely by the ratio of their widths:

\[I_{OUT} = I_{REF} \left( \frac{W_2 / L_2}{W_1 / L_1} \right)\]

To double the current, the layout engineer makes the output transistor twice as wide as the reference transistor. In practice, rather than drawing one wide transistor (which can introduce lithographic edge errors), engineers connect multiple identical "unit transistors" in parallel. For example, a 1:4 current scaling ratio uses one unit transistor for the reference and four identical unit transistors wired in parallel for the output.

Scaling in BJTs

In bipolar transistors, the collector current is directly proportional to the saturation current (\(I_S\)), which is determined by the physical area of the emitter (\(A_E\)). The scaling equation is:

\[I_{OUT} = I_{REF} \left( \frac{A_{E2}}{A_{E1}} \right)\]

Just like parallel unit MOSFETs, BJT current mirrors scale currents by placing multiple unit transistors in parallel or by fabricating a single transistor with multiple emitter fingers.

Distributing Bias Across the Chip

While a simple current mirror works locally, routing a sensitive gate-to-source voltage line across a large silicon die to bias distant circuits is problematic. Long metal traces introduce voltage drops (IR drop) in the ground return path and pick up capacitive noise from adjacent digital clocks, corrupting the \(V_{GS}\) or \(V_{BE}\) signal.

To distribute bias currents across an entire chip, engineers use a master-slave distribution scheme:

  1. A central bandgap reference generates a precise master current.
  2. A central multi-output current mirror copies and scales this master current into several intermediate bias currents.
  3. These currents (rather than voltages) are routed across the chip via long metal traces. Because the signal is a current, parasitic series resistance along the wire does not degrade the accuracy of the signal.
  4. Once the current reaches the target functional block, it feeds into a local current mirror, which converts it back into the required local bias voltages and currents for that specific stage.

Overcoming Real-World Non-Idealities

Even on a monolithic IC, basic two-transistor current mirrors suffer from physical limitations that degrade their accuracy. Designers use specific layout techniques and advanced circuit topologies to mitigate these issues:

  • Channel-Length Modulation and the Early Effect: Ideally, a current mirror has infinite output impedance, meaning the output current remains constant regardless of the voltage at the output terminal. In reality, changes in the drain-to-source voltage (\(V_{DS}\)) or collector-to-emitter voltage (\(V_{CE}\)) alter the effective width of the depletion region, causing the output current to vary. Designers fix this by using Cascode or Wilson current mirrors, which stack additional transistors on top of the mirror to shield the bottom transistors from voltage fluctuations, increasing output impedance by orders of magnitude.
  • Base Current Error (BJTs): In a BJT mirror, the reference current must supply the base currents for both transistors, leading to an output current slightly lower than the reference. Adding a buffer transistor (such as in a beta-helper or Wilson configuration) minimizes this error.
  • Process Gradients: Silicon wafer properties (like oxide thickness) change slightly from one side of the chip to the other. To prevent this linear gradient from ruining the matching of scaled transistors, layout engineers use common-centroid layouts (such as interdigitated fingers), where the unit elements of the reference and output transistors are symmetrically interwoven so they share the exact same physical center point on the die.