How Cryo-CMOS Readout Circuits Work at 4K in Quantum Computers

This article provides a comprehensive overview of how cryogenic complementary metal-oxide-semiconductor (cryo-CMOS) readout circuits operate at 4 Kelvin inside dilution refrigerators without overwhelming the system's strict thermal limits. As quantum computers scale to thousands of qubits, placing control and readout electronics close to the quantum processor becomes essential to reduce wiring complexity. To achieve this without melting the delicate quantum state, engineers rely on advanced transistor physics at cryogenic temperatures, ultra-low-power circuit topologies, frequency-division multiplexing, and duty-cycled power management to keep heat dissipation strictly beneath the 1-to-2-watt cooling budget of the 4K stage.

The 4 Kelvin Cooling Budget Challenge

In a dilution refrigerator, qubits typically operate at millikelvin temperatures (around 10 to 20 mK), where cooling power is measured in mere microwatts. Consequently, high-density control and readout electronics cannot be placed directly next to the qubits. Instead, they are positioned at the 4 Kelvin (4K) stage, which relies on pulse tube cryocoolers that offer a maximum cooling budget of roughly 1 to 2 watts. To read out thousands of qubits simultaneously, each individual cryo-CMOS readout channel must consume less than a single milliwatt of power.

Exploiting Transistor Physics at 4 Kelvin

Operating standard silicon CMOS technology at 4K fundamentally alters transistor behavior, which circuit designers exploit to drastically cut power consumption:

  • Steeper Subthreshold Swing: At 4K, thermal energy drops significantly, allowing transistors to switch on and off much more sharply than at room temperature. This steeper subthreshold slope allows circuits to operate at dramatically lower supply voltages without losing switching speed.
  • Increased Carrier Mobility: Reduced lattice vibrations (phonons) at cryogenic temperatures allow electrons to move through the silicon channel with less resistance, boosting transistor transconductance and efficiency.
  • Reduced Leakage Current: Off-state leakage currents drop precipitously at 4K, meaning static power dissipation is nearly eliminated.

However, cooling also increases the transistor threshold voltage, making it harder to turn the device on. Engineers counter this by using Fully Depleted Silicon-On-Insulator (FD-SOI) technology. FD-SOI allows a voltage to be applied to the back-gate of the transistor, dynamically lowering the threshold voltage so the circuit can run on ultra-low voltage supplies (often below 0.5V), which directly reduces dynamic power dissipation.

Ultra-Low-Power Circuit Topologies

To process the weak microwave signals returning from the qubits (after initial amplification by a travelling-wave parametric amplifier at the mK stage), the 4K readout circuit requires a Low-Noise Amplifier (LNA), a mixer for down-conversion, and an Analog-to-Digital Converter (ADC).

To stay within the thermal budget, each block is redesigned for extreme efficiency:

  • Current-Reuse LNAs: Instead of powering multiple amplifier stages separately, cryo-CMOS LNAs stack transistors on top of one another. The same bias current flows through multiple stages, amplifying the signal multiple times for the power cost of a single stage.
  • Passive Mixers: Rather than using active mixers that consume continuous DC power and generate flicker noise, designers use passive switches driven by local oscillators. This consumes zero DC power in the mixing core.
  • Successive Approximation Register (SAR) ADCs: For digitizing the readout signal, SAR ADCs are favored over flash or pipeline architectures. SAR ADCs rely on capacitive charge redistribution rather than power-hungry operational amplifiers, consuming power only when actively converting a sample.

Frequency-Division Multiplexing (FDM)

The most effective architectural strategy for saving power at the 4K stage is Frequency-Division Multiplexing. Instead of building one dedicated cryo-CMOS readout chain per qubit, multiple qubits are coupled to a single feedline using resonators tuned to slightly different frequencies.

A single wideband cryo-CMOS receiver at the 4K stage captures this combined multi-tone signal. By reading out 16, 32, or 64 qubits simultaneously through a single LNA and ADC chain, the total static and dynamic heat dissipation is amortized across dozens of qubits, lowering the effective power per qubit to tens of microwatts.

Aggressive Duty Cycling and Power Gating

Qubit readout is not a continuous process; it occurs in short bursts at the end of a quantum algorithm or during error-correction cycles. Cryo-CMOS circuits take advantage of this by implementing aggressive power gating.

Because CMOS transistors have virtually zero leakage at 4K and fast switching times, the readout receivers are completely powered down while the qubits are performing logic gates. The circuits are woken up just nanoseconds before a measurement pulse arrives and are shut off immediately after the data is digitized. This duty cycling reduces the average thermal load on the dilution refrigerator by orders of magnitude.

On-Chip Digital Decimation

Driving high-speed digital data out of the dilution refrigerator from 4K to room temperature requires driving heavy coaxial or twisted-pair cables, which consumes significant power in the I/O pad drivers. To prevent I/O power from blowing the cooling budget, cryo-CMOS readout chips integrate lightweight digital signal processing (DSP) directly at 4K.

Instead of sending raw, high-bit-rate ADC waveforms to room temperature, the 4K digital logic demodulates the signal, compares it against a threshold, and reduces the entire measurement to a single binary bit (0 or 1) representing the qubit state. Transmitting a single bit requires minimal driver power and allows the use of low-thermal-conductivity wiring, preserving the 4K cooling budget from both electrical and passive thermal loads.