How an ALU Combines Adder and Logic Blocks in Microprocessors

An Arithmetic Logic Unit (ALU) is the core execution engine inside a microprocessor, responsible for performing mathematical and logical operations on binary data. This article provides an overview of how an ALU integrates combinational adder circuits and bitwise logic blocks into a single cohesive system. By running arithmetic and logic circuits in parallel and using multiplexers controlled by operation codes (opcodes), the ALU selects the correct output in a single clock cycle while simultaneously generating status flags for the processor.

The Parallel Execution Architecture

Inside a microprocessor, the ALU does not turn off one part of its circuitry to use another. Instead, it uses a parallel combinational architecture. When two binary inputs (often referred to as Operand A and Operand B) enter the ALU, the electrical signals are split and fed into both the arithmetic block and the bitwise logic block at the exact same time.

Because these are combinational circuits, they do not rely on a clock signal to process the inputs. As soon as the voltage levels representing the binary numbers reach the gates, both the adder block and the logic block immediately compute their respective results based on propagation delay.

The Bitwise Logic Block

The bitwise logic block is the simpler of the two primary components. For a standard 32-bit or 64-bit ALU, this block consists of arrays of basic logic gates—specifically AND, OR, XOR, and NOT gates—wired in parallel for each bit position.

When Operand A and Operand B enter this block, the first bit of A and the first bit of B are fed into an AND gate, an OR gate, and an XOR gate simultaneously. This happens for all bit positions independently. There is no interaction between bit position 0 and bit position 1. Consequently, the logic block produces multiple full-width binary outputs at once: one for the AND result, one for the OR result, and so on.

The Combinational Adder Block

The arithmetic block is centered around a combinational adder circuit, such as a Ripple-Carry Adder or a faster Carry-Lookahead Adder. Unlike the logic block, the adder must pass information between bit positions in the form of a "carry" bit.

To handle more than just addition, the adder block uses clever input manipulation, primarily utilizing Two's Complement representation for subtraction. Before Operand B enters the adder, it passes through a set of XOR gates controlled by a "subtract" signal from the control unit.

  • For Addition: The control signal is 0. Operand B passes through unchanged, and the initial Carry-In (\(C_{in}\)) to the adder is set to 0. The circuit computes \(A + B\).
  • For Subtraction: The control signal is 1. The XOR gates invert all the bits of Operand B, and the initial \(C_{in}\) is set to 1. This effectively turns Operand B into its negative Two's Complement form, allowing the exact same adder circuit to compute \(A - B\) (as \(A + (-B)\)).

Combining the Blocks with Multiplexers

Since the adder block and the bitwise logic block are constantly outputting results simultaneously, the ALU needs a way to choose which result gets sent back to the CPU registers. This is achieved using a Multiplexer (MUX).

A multiplexer acts as a digital rotary switch. The outputs from the adder block, the AND gate array, the OR gate array, and the XOR gate array are all wired into the inputs of a central output MUX.

The microprocessor's Control Unit sends an "Opcode" (Operation Code) to the ALU, which acts as the selection line for the MUX. For example, if the 2-bit selection line receives 00, the MUX might route the AND block's output to the main output bus. If it receives 11, it blocks the logic results and routes the adder's output to the main bus.

Bit-Slicing: Putting It Together at the Bit Level

In practical microprocessor electronics, the ALU is often designed using a technique called "bit-slicing." Rather than building a massive 64-bit adder on one side of the chip and a 64-bit logic block on the other, engineers design a single 1-bit ALU (a slice).

A 1-bit ALU contains one full-adder, one AND gate, one OR gate, one XOR gate, and one small multiplexer. To create a 64-bit ALU, 64 of these 1-bit slices are placed side-by-side. The Carry-Out (\(C_{out}\)) of the adder in slice 0 is wired to the Carry-In (\(C_{in}\)) of the adder in slice 1. All 64 multiplexers are wired to the same opcode selection lines, ensuring every slice selects the same type of operation simultaneously.

Generating Status Flags

Finally, as the multiplexer outputs the final binary number, a secondary set of combinational gates inspects the result to generate status flags for the CPU.

  • Zero Flag: A large NOR gate checks every bit of the final MUX output. If all bits are 0, the Zero flag outputs a 1.
  • Carry Flag: This is wired directly from the final \(C_{out}\) of the combinational adder block.
  • Negative Flag: This is wired directly to the Most Significant Bit (the leftmost bit) of the MUX output, which indicates the sign of the number in Two's Complement math.
  • Overflow Flag: An XOR gate compares the carry-into and the carry-out of the final bit's adder to detect if an arithmetic result exceeded the bit-width capacity.