How AC-Coupled SerDes Lanes Scale PCIe Bandwidth

This article provides a comprehensive overview of how AC-coupled high-speed Serializer-Deserializer (SerDes) lanes scale bandwidth across successive PCI Express (PCIe) generations in modern computing electronics. It covers the fundamental role of SerDes architecture, the necessity of AC coupling for signal integrity, the evolution of encoding schemes, the transition from NRZ to PAM4 modulation, and the advanced equalization techniques required to achieve multi-gigabit data rates.

The Role of SerDes in PCI Express

PCI Express relies on high-speed Serializer-Deserializer (SerDes) architecture to move data between processors, memory, and peripherals. Earlier computing buses used parallel connections, which suffered from clock skew—where signals on different traces arrive at slightly different times—limiting maximum clock speeds.

SerDes overcomes this by converting parallel data inside a chip into a high-speed serial stream transmitted over a single differential pair of traces (a lane). At the receiving end, the SerDes converts the serial stream back into parallel data. Because the clock signal is embedded directly within the serial data stream and recovered by a Clock and Data Recovery (CDR) circuit, PCIe can scale frequencies significantly without worrying about timing skew across wide buses. Multiple SerDes lanes can be bonded together (x1, x4, x8, x16) to multiply total bandwidth linearly.

Why AC Coupling is Essential

Every PCIe SerDes lane uses AC coupling, achieved by placing tiny series capacitors along the transmit path. AC coupling serves three primary functions in scaling high-speed links:

  1. Common-Mode Voltage Isolation: Transmitters and receivers are often manufactured on different silicon process nodes and operate at different core voltages. AC coupling blocks the DC component of the signal, allowing a transmitter and receiver with entirely different DC voltage levels to communicate safely.
  2. Signal Integrity: By stripping the DC offset, the receiver can establish its own optimal DC bias point, maximizing the performance of its internal amplifiers and equalizers.
  3. Hot-Plug Protection: Capacitors provide electrical isolation that protects sensitive transceiver circuitry when cards are inserted or removed in enterprise server environments.

To prevent the AC-coupling capacitors from accumulating a net charge (which causes baseline wander and bit errors), the transmitted data must be DC-balanced, meaning it contains an equal number of logical ones and zeros over time.

Doubling Data Rates: Frequencies and Encoding

A hallmark of PCI Express is its commitment to doubling the bandwidth per lane with each new generation while maintaining backward compatibility. Early generations achieved this through raw frequency scaling and more efficient encoding schemes.

  • PCIe 1.0 and 2.0: Utilized 8b/10b encoding, which mapped 8-bit data bytes into 10-bit symbols. While this guaranteed DC balance for the AC-coupled capacitors and provided enough signal transitions for the CDR circuit, it introduced a 20% bandwidth overhead. PCIe 1.0 operated at 2.5 GT/s (Gigatransfers per second), and PCIe 2.0 doubled the clock rate to 5.0 GT/s.
  • PCIe 3.0, 4.0, and 5.0: To scale to 8.0 GT/s in PCIe 3.0 without immediately requiring exotic circuit board materials, the specification switched to 128b/130b encoding. This reduced the encoding overhead from 20% to approximately 1.5%, providing a massive jump in usable bandwidth. Data scrambling was introduced to maintain the DC balance required by the AC coupling capacitors. PCIe 4.0 and 5.0 subsequently doubled the transfer rates to 16.0 GT/s and 32.0 GT/s respectively, pushing the limits of traditional copper traces.

The Shift from NRZ to PAM4 Modulation

From PCIe 1.0 through PCIe 5.0, SerDes lanes relied on Non-Return-to-Zero (NRZ) signaling. NRZ uses two voltage levels to represent a logical 0 or 1, transmitting one bit per clock cycle. However, at the 64.0 GT/s target of PCIe 6.0, doubling the Nyquist frequency again under NRZ would cause severe signal attenuation (insertion loss) across standard printed circuit boards (PCBs), turning the signal into unreadable noise.

To scale bandwidth to 64.0 GT/s (PCIe 6.0) and 128.0 GT/s (PCIe 7.0), the SerDes architecture transitioned to Pulse Amplitude Modulation 4-level (PAM4). PAM4 uses four distinct voltage levels to transmit two bits of data per clock cycle (00, 01, 10, 11). This allows PCIe 6.0 to double the data rate over PCIe 5.0 while keeping the fundamental channel frequency the same.

Because PAM4 packs four voltage levels into the same voltage swing previously used by two, the "eyes" of the signal are three times smaller, making the AC-coupled lane much more susceptible to noise. To compensate, PCIe 6.0 introduced lightweight Forward Error Correction (FEC) and Flow Control Unit (FLIT) encoding to detect and correct bit errors on the fly without adding significant latency.

Combating Signal Loss with Advanced Equalization

As SerDes frequencies climb, the PCB traces and AC-coupling capacitors act as a low-pass filter, degrading high-frequency signals and causing Inter-Symbol Interference (ISI), where one bit bleeds into the next. Scaling bandwidth requires sophisticated equalization built directly into the SerDes silicon:

  • Transmitter De-emphasis/Pre-shoot: The transmitter intentionally alters the amplitude of bits following a transition to counteract the expected loss in the copper trace.
  • Continuous-Time Linear Equalization (CTLE): Located at the receiver, CTLE acts as a high-pass filter that boosts high-frequency components of the incoming signal relative to the low frequencies.
  • Decision Feedback Equalization (DFE): A non-linear equalizer in the receiver that uses the history of previously detected bits to calculate and subtract the ISI from the currently arriving bit.

By combining AC-coupled differential signaling, efficient encoding, PAM4 modulation, and active silicon equalization, SerDes lanes successfully overcome the physical limitations of copper interconnects to double PCIe bandwidth generation after generation.