How a Demultiplexer Routes Serial Data to Multiple Channels

This article explains the mechanics of a demultiplexer (DEMUX) and how it distributes a single serial data source across multiple selectable destination channels in electronic circuits. You will learn about the core components of a demultiplexer, including the data input, selection lines, and output channels, as well as the internal logic gates that make data routing possible. Additionally, this guide covers how timing and address selection work together to convert a single stream of serial data into parallel outputs for various digital systems.

The Core Function of a Demultiplexer

A demultiplexer, often abbreviated as DEMUX, is a combinational logic circuit designed to take a single input signal and route it to one of several digital output lines. It acts as a high-speed electronic rotary switch. While a multiplexer combines multiple inputs into one output, a demultiplexer performs the exact opposite operation, making it essential for serial-to-parallel data conversion.

Key Components of a DEMUX

To understand how data distribution occurs, it is necessary to look at the three primary pin groups on a standard demultiplexer chip:

  1. Single Data Input: This is the entry point for the serial data stream. The signal consists of a continuous sequence of binary bits (1s and 0s) arriving one after another.
  2. Control or Selection Lines: These inputs determine which output channel will receive the incoming data. The number of selection lines dictates the total number of available output channels. This follows the binary rule of \(2^n\), where \(n\) is the number of selection lines. For example, 2 selection lines can control 4 outputs (\(2^2 = 4\)), and 3 selection lines can control 8 outputs (\(2^3 = 8\)).
  3. Multiple Output Channels: These are the destination pathways. Only one output channel is active at any given moment, while all other outputs are held in an inactive state (typically logic low, or 0).

How Selection Lines Route the Data

The distribution of the serial data relies on binary addressing applied to the selection lines. Inside the demultiplexer, an array of AND gates and NOT gates (inverters) decodes the binary address provided by the selection lines.

Every output channel is connected to its own internal AND gate. Each of these AND gates receives the main serial data input, as well as a unique combination of the selection line signals.

Consider a 1-to-4 demultiplexer with one data input (\(D\)), two selection lines (\(S_1\) and \(S_0\)), and four outputs (\(Y_0, Y_1, Y_2, Y_3\)):

  • State 00: When \(S_1 = 0\) and \(S_0 = 0\), the internal logic enables the AND gate connected to \(Y_0\). The serial data at \(D\) passes directly through to \(Y_0\). Outputs \(Y_1, Y_2,\) and \(Y_3\) output a 0.
  • State 01: When \(S_1 = 0\) and \(S_0 = 1\), the path to \(Y_0\) closes, and the AND gate for \(Y_1\) is enabled. The data stream now flows exclusively to \(Y_1\).
  • State 10: When \(S_1 = 1\) and \(S_0 = 0\), the data is routed solely to output \(Y_2\).
  • State 11: When \(S_1 = 1\) and \(S_0 = 1\), the data is routed solely to output \(Y_3\).

Because the active AND gate takes the serial data as one of its inputs, its output will mirror the exact state of the data line. If the data line is high (1), the selected output goes high. If the data line is low (0), the selected output goes low.

Distributing Continuous Serial Data (Time-Division Demultiplexing)

To distribute a continuous serial data source—such as a communication line carrying interleaved data for four different devices—the selection lines must be synchronized with the incoming data stream. This process is known as Time-Division Demultiplexing.

A system clock and a binary counter are typically connected to the selection lines of the demultiplexer. As the serial data arrives bit by bit (or packet by packet), the counter increments the binary address on the selection lines in strict synchronization with the data rate:

  1. Bit 1 arrives at the data input while the counter sets the select lines to 00. Bit 1 goes to Channel 0.
  2. Bit 2 arrives just as the counter increments the select lines to 01. Bit 2 goes to Channel 1.
  3. Bit 3 arrives as the select lines change to 10. Bit 3 goes to Channel 2.
  4. Bit 4 arrives as the select lines change to 11. Bit 4 goes to Channel 3.
  5. The counter resets to 00 for Bit 5, sending it to Channel 0, and the cycle repeats.

By switching the selection lines at the exact frequency of the incoming bits, the demultiplexer successfully unpacks a single high-speed serial stream into multiple slower, independent data channels.

Holding the Data State

In standard combinational demultiplexers, once the selection lines switch to a new address, the previous output channel immediately drops back to a logic 0. In applications where the destination channels need to retain the value of the bit they just received while the DEMUX services other channels, an addressable latch is used. This variation of the demultiplexer includes internal memory elements (flip-flops) on each output, allowing the circuit to distribute serial data and hold those states simultaneously across all parallel outputs.