What Is Single-Link DVI’s Max Pixel Clock?

The maximum pixel clock frequency officially supported by the single-link Digital Visual Interface (DVI) specification is 165 MHz. This article examines the technical architecture behind that limit, explains how Transition-Minimized Differential Signaling (TMDS) handles video data, details the maximum resolutions and refresh rates achievable within this bandwidth, and highlights how display blanking intervals influence what a single-link connection can output.

The Technical Specification: 165 MHz and TMDS

Defined in 1999 by the Digital Display Working Group (DDWG) in the DVI 1.0 specification, single-link DVI relies on Transition-Minimized Differential Signaling (TMDS). A single-link DVI connection uses three data channels (one each for red, green, and blue) alongside a dedicated differential clock channel.

The clock channel runs at the pixel clock rate, capped at a maximum frequency of 165 MHz. Because TMDS utilizes an 8b/10b encoding scheme, each 8-bit color component is encoded into a 10-bit symbol per clock cycle to maintain DC balance and minimize signal transitions across the copper cable. At 165 MHz:

• 10 bits per channel are transmitted per clock cycle across each of the 3 data channels.
• Each data line operates at a bit rate of 1.65 Gbps (\(165\text{ MHz} \times 10\text{ bits}\)).
• Across all three color channels, the raw transmission rate reaches 4.95 Gbps.
• Subtracting the 8b/10b coding overhead yields a maximum usable video payload throughput of 3.96 Gbps (\(165\text{ megapixels/second} \times 24\text{ bits/pixel}\)).

Resolution and Refresh Rate Capabilities

Because the limit is bound strictly to the 165 MHz pixel clock rather than a fixed grid of pixels, any resolution and refresh rate combination whose pixel clock requirement remains at or below 165 MHz can operate over a standard single-link connection.

Under standard VESA Coordinated Video Timings (CVT) and Generalized Timing Formula (GTF) standards, single-link DVI easily accommodates common legacy and widescreen resolutions:

• 1920 × 1080 (1080p) at 60 Hz: Typically requires a pixel clock of approximately 148.5 MHz under standard blanking intervals.
• 1920 × 1200 (WUXGA) at 60 Hz: Requires approximately 154 MHz when using VESA Reduced Blanking (CVT-RB). Under standard CRT-era blanking, this resolution exceeds 165 MHz and requires dual-link DVI.
• 1600 × 1200 (UXGA) at 60 Hz: Requires roughly 162 MHz under standard timings, fitting just under the 165 MHz threshold.
• 1280 × 1024 (SXGA) at 75 Hz or 85 Hz: Operates comfortably within the 108 MHz to 157.5 MHz range.

Higher resolutions, such as 2560 × 1440 (QHD) or 2560 × 1600 (WQXGA) at 60 Hz, require clock rates well above 200 MHz, necessitating a dual-link DVI connection that adds three more TMDS data pairs to double throughput.

The Role of Reduced Blanking

The pixel clock counts not just active visible pixels, but also blanking intervals—the inactive time allocated between horizontal scan lines and vertical refresh frames originally required by CRT electron guns.

On modern flat panels, these large pauses are unnecessary. The VESA Reduced Blanking standard shrinks non-visible overhead substantially. By reducing the number of idle cycles transmitted each second, display controllers can push higher active resolutions without crossing the 165 MHz single-link ceiling, making 1920 × 1200 at 60 Hz viable on standard single-link hardware.