Phase-Locked Loops in DVI Pixel Clock Recovery

In Digital Visual Interface (DVI) systems, accurate video transmission depends on the receiver's ability to precisely sample incoming high-speed serial data. Because DVI transmits a reference pixel clock at one-tenth of the actual bit rate rather than embedding the clock inside the data lines, a Phase-Locked Loop (PLL) at the receiver is essential. This article explains how the PLL acts as a frequency multiplier, phase aligner, and jitter filter to reconstruct the high-speed bit clock and the stable pixel clock required for proper video deserialization.

The TMDS Clock Architecture

DVI relies on Transition-Minimized Differential Signaling (TMDS) across four differential pairs: three carry serial red, green, and blue video data, while the fourth carries a continuous reference clock. Unlike modern display standards that embed the clock within the data stream, DVI separates them.

TMDS encodes each 8-bit color component into a 10-bit character to balance DC bias and minimize signal transitions. As a result, ten serial data bits are transmitted per channel for every single pixel clock cycle. To save transmission bandwidth and reduce electromagnetic interference (EMI), the physical clock channel carries only the base 1x pixel clock (ranging from 25 MHz to 165 MHz in single-link DVI), rather than the full 10x bit-rate clock.

Frequency Multiplication

The primary role of the PLL in the DVI receiver is frequency multiplication. The deserialization hardware requires a high-speed bit-rate clock operating at ten times the frequency of the transmitted pixel clock.

Inside the PLL:

  1. A voltage-controlled oscillator (VCO) generates a high-speed internal clock.
  2. A divide-by-10 feedback divider scales down this generated clock.
  3. A phase detector compares the divided signal with the incoming reference clock from the cable.
  4. A charge pump and loop filter adjust the VCO's control voltage until the frequency and phase match the input.

By multiplying the reference clock by a factor of 10, the PLL produces the localized bit clock (up to 1.65 GHz in single-link configurations) needed to latch individual bits.

Phase Alignment and Skew Compensation

Beyond multiplication, the PLL aligns the phase of the internal sampling clock with the incoming data streams. Cables, connectors, and board traces introduce delay and phase shifts between the clock channel and the data channels (inter-pair skew).

The PLL dynamically adjusts the phase of the generated bit-rate clock to place the sampling strobe directly in the center of each incoming data bit's "eye diagram." Some advanced DVI receivers use multi-phase PLLs or combine the main PLL with delay-locked loops (DLLs) on individual data channels to adjust for channel-to-channel timing variations independently.

Jitter Filtering

Signal degradation over copper cables introduces high-frequency jitter onto the reference clock. If passed directly to the sampling circuits, this timing instability would cause bit errors and visual artifacts such as pixel noise or dropped frames.

The loop filter within the PLL acts as a low-pass filter for phase variations. It suppresses high-frequency jitter present on the incoming clock line, allowing the VCO to generate a clean, stable internal clock that tracks only the low-frequency, intentional drift of the video source.

Driving Deserialization

Once the PLL locks to the incoming signal, it delivers two synchronized clocks to the receiver logic: the 10x serial bit clock and the recovered 1x parallel pixel clock. The 10x clock drives the shift registers that sample and shift in the serial bits from the three TMDS data lanes. Once ten bits are gathered, the recovered 1x pixel clock latches the entire 10-bit parallel word into the TMDS decoder, where it is converted back into uncompressed 8-bit RGB color data for the display panel.