PCB Stackup and Differential Impedance in DVI Routing

Digital Visual Interface (DVI) video transmission relies on high-speed Transition Minimized Differential Signaling (TMDS), which mandates a tightly controlled 100-ohm differential impedance. The PCB layer stackup directly governs this impedance by defining the dielectric constant, the thickness of the dielectric layers, and the physical distance between the signal traces and their reference planes. Designing an optimized stackup ensures stable electromagnetic coupling, minimizes signal reflections, suppresses electromagnetic interference (EMI), and preserves signal integrity across all DVI data and clock lanes.

The 100-Ohm Impedance Requirement in DVI

DVI video channels transmit high-speed digital video using four differential pairs: three color channels (Red, Green, Blue) and one clock channel. The DVI specification mandates that these TMDS pairs maintain a differential impedance (\(Z_{diff}\)) of 100 ohms \(\pm 10\%\). Deviations from this target cause impedance discontinuities, leading to signal reflections, reduced eye diagram openings, jitter, and display artifacts or complete loss of sync at high resolutions.

Dielectric Thickness and Reference Plane Distance

In any PCB stackup, the dielectric thickness (\(H\))—the height between the signal layer and the adjacent reference plane—is the most sensitive parameter influencing impedance:

Thinner Dielectrics: Placing a signal layer closer to an unbroken reference ground plane increases trace-to-plane capacitance, which lowers both single-ended and differential impedance.
Thicker Dielectrics: Increasing the height lowers capacitance and raises impedance, requiring wider traces to bring the impedance back down to 100 ohms.

Controlling the prepreg and core thickness directly enables the designer to balance trace width with the physical routing constraints of DVI connector pinouts.

Trace Geometry and Inter-Trace Coupling

Differential impedance is a function of odd-mode impedance (\(Z_{diff} = 2 \times Z_{odd}\)), which depends on the coupling between the two traces of a pair:

Trace Spacing (\(S\)): Bringing the two traces closer together increases mutual capacitive and inductive coupling, reducing differential impedance.
Trace Width (\(W\)): Wider traces increase capacitance to the reference plane, decreasing impedance.
Aspect Ratio in the Stackup: If the stackup specifies a thick dielectric, maintaining 100 ohms requires either excessively wide traces or wider spacing, which consumes valuable board space and complicates escape routing under high-density DVI connectors. A stackup with a thinner dielectric (e.g., 3 to 5 mils) allows for narrower traces and tighter spacing (e.g., a 4/4 or 5/5 mil width/spacing rule), which closely matches connector pad pitch.

Dielectric Constant (\(D_k\)) and Material Selection

The relative permittivity (\(D_k\)) of the substrate material dictates the phase velocity of the TMDS signals and influences trace capacitance. Standard FR-4 typically has a \(D_k\) between 4.2 and 4.5, while high-frequency laminates feature a lower \(D_k\) (around 3.5 to 3.8).

A higher \(D_k\) increases capacitance and lowers impedance for a given geometry. When formulating the stackup, engineers must account for the effective \(D_k\), especially when using core versus prepreg layers, as resin content variations across the stackup can alter the actual impedance of the differential pairs.

Microstrip vs. Stripline Configurations

The stackup determines whether DVI traces are routed as microstrip (outer layers) or stripline (inner layers):

Surface Microstrip (Top/Bottom Layers): Traces are referenced to a single ground plane beneath them and are surrounded by air and solder mask on top. This configuration provides faster propagation velocities and avoids layer-transition vias, but it exposes TMDS signals to ambient noise and radiates more EMI.
Symmetrical/Asymmetrical Stripline (Internal Layers): Traces are sandwiched between two reference ground planes. Stripline configurations provide superior shielding against EMI and cross-talk. However, having two ground planes significantly increases capacitance, meaning traces must be designed narrower to maintain the target 100-ohm impedance compared to a surface microstrip.

Return Paths and Reference Plane Continuity

Differential signals still require a continuous reference plane to carry high-frequency return currents. The layer stackup must place a dedicated, unbroken Ground (GND) plane immediately adjacent to every DVI routing layer.

Referencing a high-speed TMDS pair to a power plane or routing across plane splits creates severe impedance discontinuities and loop inductance. If a DVI pair must change layers within the stackup, the stackup should provide ground layers on both target layers, supplemented with ground return vias placed immediately adjacent to the signal vias to keep the return loop small and maintain impedance stability.