How DVI Prevents DC Bias on Transmission Lines

Digital Visual Interface (DVI) prevents direct current (DC) bias on its differential transmission lines by utilizing Transition Minimized Differential Signaling (TMDS) with an integrated 8b/10b encoding scheme. By continuously tracking the cumulative count of transmitted ones and zeros—a metric known as running disparity—the TMDS transmitter dynamically inverts data words to maintain an equal ratio of high and low signal states over time. This active balancing prevents charge accumulation across the differential lines, eliminates signal baseline wander, and ensures reliable signal decoding at the receiver.

The Problem of DC Bias in High-Speed Data

In high-speed differential transmission, signals are transmitted as voltage differences between two complementary conductors. If a data stream contains significantly more logical ones than zeros (or vice versa) over an extended period, a net direct current develops across the link.

This DC bias creates severe transmission problems:

  • Baseline Wander: The average DC voltage drifts, shifting the reference threshold and causing the receiver to misinterpret bit transitions.
  • Capacitor Saturation: Many differential systems use AC-coupling capacitors to isolate ground loops and different supply voltages. A sustained DC bias charges these capacitors, distorting the signal waveforms.
  • Increased Electromagnetic Interference (EMI): Unequal current flow unbalances the differential pair, compromising the natural noise-canceling properties of differential signaling.

The TMDS 8b/10b Encoding Mechanism

To eliminate DC bias, DVI uses TMDS encoders that convert standard 8-bit pixel data into 10-bit symbols before transmission across the differential channels (Red, Green, Blue, and Clock). This encoding takes place in two sequential stages:

1. Transition Minimization (The 9th Bit)

The encoder first determines whether an XOR or XNOR operation will result in fewer logical transitions (switching from 0 to 1, or 1 to 0). Minimizing transitions lowers the high-frequency content of the signal, thereby reducing EMI.

The 9th bit is added to the byte to signal to the receiver whether XOR or XNOR logic was applied, allowing the receiver to reconstruct the original 8-bit data.

2. DC Balancing via Running Disparity (The 10th Bit)

The final stage of the encoder enforces DC balance. The transmitter maintains an internal counter called the Running Disparity, which represents the cumulative historical difference between the total number of transmitted ones and zeros.

When preparing to send a 10-bit symbol, the encoder evaluates:

  1. The current state of the Running Disparity counter (positive, negative, or neutral).
  2. The number of ones versus zeros in the candidate 9-bit word.

If transmitting the candidate word without alteration would push the running disparity further away from zero, the encoder inverts the first eight bits of the symbol. It then sets the 10th bit to 1 to indicate that an inversion occurred. If transmitting the word naturally pulls the running disparity back toward zero (or keeps it neutral), the encoder leaves the data un-inverted and sets the 10th bit to 0.

Once the decision is made, the running disparity counter is updated to reflect the new cumulative balance.

Control and Blanking Periods

Video streams contain periodic blanking intervals (horizontal and vertical sync periods) where no active pixel data is sent. DVI handles these intervals using dedicated 10-bit control characters representing sync signals (HSYNC and VSYNC).

The TMDS standard assigns four specific, high-transition 10-bit patterns to these control states. Each of these control tokens contains an equal distribution of zeros and ones or operates in complementary pairs, ensuring that the link remains perfectly DC-balanced even when active video frames are not being transmitted.

Result at the Receiver

Because the TMDS encoder continuously drives the net DC voltage to zero, the differential signal stays centered around the common-mode voltage. When the differential pair arrives at the receiver, the termination resistors and differential amplifiers can recover the clock and data accurately without experiencing signal degradation caused by baseline drift.