How DVI Implements EDID Communication

This article explains how the Digital Visual Interface (DVI) communicates Extended Display Identification Data (EDID) between a computer and a monitor. It covers the physical pinout used for data transmission, the underlying I2C protocol, the role of the Display Data Channel (DDC), and the sequence of events that allows an operating system to automatically detect and configure display settings.

The Physical Layer: Dedicated DDC Pins

DVI establishes EDID communication through an auxiliary channel separate from the Transition-Minimized Differential Signaling (TMDS) channels that carry the actual video stream. This channel relies on the VESA Display Data Channel (specifically DDC2B) standard and utilizes four dedicated pins on the DVI connector:

  • Pin 6 (DDC Clock / SCL): The clock line that synchronizes serial data transfer.
  • Pin 7 (DDC Data / SDA): The bidirectional data line that carries the request and transmission bits.
  • Pin 14 (+5V Power): A 5-volt power feed provided by the computer's graphics card.
  • Pin 15 (Ground): The ground reference for the +5V supply and the DDC signals.

In addition to these pins, Pin 16 (Hot Plug Detect / HPD) plays a vital role by signaling to the host system that a display has been connected.

The Communication Protocol: I2C and DDC2B

EDID transfer operates over the standard I2C (Inter-Integrated Circuit) two-wire serial bus. In this relationship:

  • The computer's graphics processing unit (GPU) acts as the I2C Master.
  • An EEPROM chip inside the monitor acts as the I2C Slave.

The monitor's EDID EEPROM is assigned a standardized 7-bit I2C slave address of 0x50 (represented as 0xA0 for write operations and 0xA1 for read operations in 8-bit notation).

Because the computer supplies +5V power via Pin 14, the monitor's EEPROM chip can be powered and read even when the monitor is turned off or unplugged from an AC power outlet, ensuring the operating system can always identify the display hardware.

Step-by-Step EDID Retrieval Process

  1. Connection and Detection: When the DVI cable is plugged in, the monitor asserts a high signal (typically around +5V via a pull-up resistor) on the Hot Plug Detect line (Pin 16).
  2. Read Request Initiation: Detecting the voltage change on the HPD pin, the host graphics driver generates a start condition on the I2C bus (pulling SDA low while SCL is high) and transmits the address 0x50 along with a write command to set the memory offset to 0x00.
  3. Data Transmission: The host restarts the bus and issues a read command (0xA1). The monitor's EEPROM acknowledges the request and begins clocking out the EDID data byte-by-byte across Pin 7 in sync with the clock pulses provided by the GPU on Pin 6.
  4. Data Validation: The host receives the baseline 128-byte data block (or 256 bytes if CEA-861 extension blocks are present). The graphics driver verifies the block's integrity using an 8-bit checksum stored in the final byte.
  5. Display Configuration: Once verified, the graphics driver parses the data—extracting supported native resolutions, refresh rates, color profiles, and timing parameters—and configures the digital TMDS links to drive the display at an optimal, supported video mode.