How DVI Hot Plug Detection Works

Hot-Plug Detection (HPD) on a Digital Visual Interface (DVI) allows a computer's graphics hardware to detect the connection or removal of a display dynamically without requiring a system reboot. This article breaks down the physical pin architecture, voltage signaling, and communication protocols that enable a source device to identify a monitor, read its configuration data, and instantly begin transmitting video signals.

The Physical Interface and Voltage States

The DVI specification reserves specific pins within the 24-pin digital connector layout to handle the hot-plug state. The two critical pins governing this process are:

  • Pin 14 (+5V Power): Supplied by the video source (graphics card) to power the display's internal identification circuitry.
  • Pin 16 (Hot Plug Detection): Driven by the sink device (monitor) back to the source to indicate connection status.

When no monitor is attached, the source device maintains a weak pull-down resistor on Pin 16, keeping the voltage at logic low (0V). Once connected, the host supplies a +5V current across Pin 14 to the monitor. In response, the monitor asserts a logic high signal—typically between +2.4V and +5V—back across Pin 16 to the host device using an internal pull-up resistor.

The Interrupt and Handshake Sequence

The transition from a low voltage to a high voltage on Pin 16 triggers an immediate hardware interrupt within the graphics controller. This initiates a sequence to establish the video link:

  1. Hardware Interrupt: The host graphics card registers the logic high voltage on Pin 16, alerting the operating system's display driver that a sink device is attached and powered.
  2. DDC Query: The graphics card initiates communication via the Display Data Channel (DDC), utilizing Pin 6 (DDC Clock) and Pin 7 (DDC Data). This interface operates as a standard I2C bus.
  3. Reading the EDID: Powered by the +5V rail from Pin 14, the monitor's internal EEPROM transmits its Extended Display Identification Data (EDID) to the host. The EDID contains crucial specifications, such as supported native resolutions, refresh rates, pixel clock limits, and color profile capabilities.
  4. Link Activation: The graphics processor analyzes the EDID, configures the appropriate display mode, and activates the Transition-Minimized Differential Signaling (TMDS) data lanes to transmit the video stream.

Disconnection Detection

When the user unplugs the DVI cable or turns off the display, the voltage on Pin 16 drops back to logic low (0V). The host controller detects this drop, immediately ceases the TMDS signal output, and signals the operating system to reallocate system resources, such as reverting to a primary display or adjusting multi-monitor desktop configurations.