How DVI Handles Progressive vs Interlaced Video Timing

A Digital Visual Interface (DVI) receiver processes progressive and interlaced video by decoding raw pixel clocks and synchronization pulses transmitted over Transition-Minimized Differential Signaling (TMDS) channels. While progressive signals deliver complete frames sequentially with fixed horizontal and vertical sync relationships, interlaced video delivers alternating odd and even fields differentiated by half-line timing offsets. By measuring the precise phase relationship between Horizontal Sync (HSync) and Vertical Sync (VSync), the DVI receiver identifies the scan format, determines field polarity, and routes the data to internal buffers for direct display or deinterlacing.

TMDS Signaling and Sync Decoding

DVI relies on three TMDS data lanes and one dedicated clock lane. Video timing is dictated by control tokens transmitted during the blanking intervals when the Data Enable (DE) signal is low. These tokens encode the horizontal and vertical synchronization states:

  • HSync: Defines the boundary and line rate of individual raster lines.
  • VSync: Defines the boundary and refresh rate of frames or fields.
  • DE (Data Enable): High only during active pixel data transmission; low during horizontal and vertical blanking intervals.

The receiver's phase-locked loop (PLL) locks onto the TMDS clock, allowing the digital logic to continuously monitor the state and edge transitions of HSync, VSync, and DE.

Progressive Video Handling

In a progressive video stream (such as 720p or 1080p), the receiver encounters a continuous sequence of complete frames:

  • Sync Alignment: VSync transitions maintain a static, identical phase alignment relative to HSync for every single frame. The VSync pulse consistently falls at the beginning of a horizontal blanking interval.
  • Line Counting: The number of active video lines per frame between successive VSync assertions is constant and matches the native vertical resolution.
  • Pixel Streaming: The receiver maps the incoming active data directly to the display pipeline line by line. Since modern digital displays (LCD, OLED) are natively progressive, minimal processing is required beyond color conversion and scaling.

Interlaced Video Handling

Interlaced video formats (such as 1080i) split each frame into two distinct, vertically interleaved fields: Field 1 (odd lines) and Field 2 (even lines). Handling this timing requires the receiver to identify alternating line offsets:

  • Half-Line Timing Offset: Because an interlaced frame contains an odd number of total lines (including blanking), each field contains a fractional line count ending in a half-line period (\(0.5 \times H\)).
  • Field 1 (Odd Field): VSync transitions simultaneously with the leading edge of HSync.
  • Field 2 (Even Field): VSync transitions exactly halfway through the horizontal line period relative to HSync.

Field Detection and Processing Architecture

To correctly parse interlaced video, modern DVI receiver architectures implement dedicated timing logic:

  1. Phase Comparison Counter: An internal counter clocked by the pixel clock measures the duration between the leading edge of HSync and the leading edge of VSync. If the counter detects a consistent zero-offset, the signal is locked as progressive. If the duration alternates between zero and half a line period, the receiver flags the incoming stream as interlaced.
  2. Field Identification: The phase relationship directly sets a field identification bit (Field 1 vs. Field 2) in the receiver's status registers. This bit informs downstream hardware which lines (odd or even) are currently arriving.
  3. Deinterlacing and Buffering: Unlike CRTs, modern digital panels cannot scan lines natively in fields. The DVI receiver's output is routed to a video processing unit where consecutive fields are written to an external frame buffer (SDRAM). Deinterlacing algorithms—ranging from simple spatial weaving or bobbing to motion-adaptive temporal filtering—reconstruct full progressive frames at the native panel refresh rate.