How DVI Encodes Blanking Intervals Over TMDS

Digital Visual Interface (DVI) relies on Transition Minimized Differential Signaling (TMDS) to transmit high-speed digital video streams over physical copper links. Rather than carrying pixel data continuously, the interface alternates between active video periods and blanking intervals. This article explains how horizontal blanking intervals (HBI) and vertical blanking intervals (VBI) are structured and encoded across the three primary TMDS data channels, detailing the mapping of synchronization signals into specialized 10-bit control characters.

Active Video vs. Control Periods

A standard single-link DVI connection consists of four differential pairs: three data channels (Channels 0, 1, and 2) and one dedicated clock channel. The TMDS transmitter operates in one of two fundamental operating states:

  1. Video Data Period: Active pixel values (8 bits per channel) are encoded into 10-bit TMDS characters designed to minimize signal transitions and maintain DC balance.
  2. Control Period (Blanking): During horizontal and vertical blanking, active pixel transmission stops. Instead of video data, the transmitter encodes 2-bit control signals per channel into specialized 10-bit control characters.

Both the Horizontal Blanking Interval (between active lines) and the Vertical Blanking Interval (between active frames) are transmitted strictly as Control Periods.

Channel Allocation for Control Signals

During blanking, each of the three TMDS data channels accepts a 2-bit input (\(C0, C1\)) on every pixel clock cycle. These 2-bit signals represent display synchronization and interface control lines:

  • Channel 0: Carries Horizontal Sync (HSync on \(C0\)) and Vertical Sync (VSync on \(C1\)).
  • Channel 1: Carries control signals \(CTL0\) (on \(C0\)) and \(CTL1\) (on \(C1\)).
  • Channel 2: Carries control signals \(CTL2\) (on \(C0\)) and \(CTL3\) (on \(C1\)).

In basic DVI-D implementations, Channels 1 and 2 typically tie their control bits to logical 00, as \(CTL0\) through \(CTL3\) are primarily reserved for protocol extensions (such as HDCP signaling or HDMI preambles). Consequently, Channel 0 is the primary vehicle for defining the boundaries of HBI and VBI via standard raster timing.

The 10-Bit Control Character Encoding

While active video uses transition-minimization logic (employing XOR/XNOR operations) to reduce electromagnetic interference, blanking periods intentionally discard minimization. Instead, the 2-bit control inputs are mapped to four predefined 10-bit control tokens that maximize transitions.

The four standard 10-bit control characters are:

  • 00 \(\rightarrow\) 1101010100 (or 0010101011 depending on starting bit order/polarity)
  • 01 \(\rightarrow\) 0010101011
  • 10 \(\rightarrow\) 0101010100
  • 11 \(\rightarrow\) 1010101011

These sequences are specifically selected for three key functional reasons:

  1. High Transition Density: Each character contains seven signal transitions. This rapid edge switching provides the Phase-Locked Loop (PLL) in the receiver with continuous frequency and phase references, preventing clock drift during blanking.
  2. Word Boundary Alignment: These control tokens are asymmetric and completely distinct from any valid active video 10-bit character. The receiver's deserializer uses these unique patterns to establish and lock onto 10-bit word boundaries (character framing).
  3. Inherent DC Balancing: Each pair of control symbols is balanced in terms of high and low states, maintaining baseline DC balance across the differential pair without requiring a running disparity accumulator.

Distinguishing Horizontal and Vertical Blanking

From an encoding standpoint, TMDS does not have separate "HBI" and "VBI" command packets. Instead, blanking intervals are defined purely by the state of HSync and VSync transmitted on Channel 0:

  • Horizontal Blanking (HBI): At the end of an active line, the transmitter switches from pixel encoding to control character encoding. Channel 0 transmits the control token for C0=0, C1=0 (front porch), transitions to C0=1, C1=0 (active HSync pulse), and returns to C0=0, C1=0 (back porch) before the next line of pixels begins.
  • Vertical Blanking (VBI): At the end of a field or frame, the transmitter enters a sustained Control Period across hundreds of line periods. Channel 0 continues to output periodic HSync transitions, but asserts VSync (C1=1) during the vertical sync window.

Because both intervals use the exact same four-token control mechanism, the display receiver decodes raster timing identically to an analog CRT or VGA interface, reconstructing line and frame sync based on the decoded values of Channel 0.