How DVI Decodes 10-Bit TMDS to 8-Bit Color

A DVI (Digital Visual Interface) receiver converts 10-bit Transition-Minimized Differential Signaling (TMDS) symbols back into original 8-bit color bytes through a hardware pipeline consisting of clock recovery, word alignment, and arithmetic inverse-logic decoding. After recovering the bit clock and aligning the serial bitstream into distinct 10-bit parallel words, the receiver checks whether the incoming symbol is a control code or active pixel data. For pixel data, it evaluates the two upper signaling bits to undo the DC-balancing inversion and reverse the transition-minimizing XOR or XNOR encoding, accurately reconstructing the original 8-bit red, green, or blue color component.

Step 1: Clock Multiplication and Deserialization

The transmission begins over three differential data lanes alongside a dedicated differential clock lane. The DVI clock lane runs at the pixel clock frequency, which represents the symbol rate rather than the raw bit rate.

  1. Clock Recovery: A Phase-Locked Loop (PLL) inside the receiver locks onto the pixel clock and multiplies its frequency by 10 to match the incoming serial bit rate.
  2. Deserialization (SerDes): Using this multiplied clock, a serial-to-parallel converter samples the high-speed differential signal and shifts the serial stream into a 10-bit parallel register once per pixel clock cycle.

Step 2: Symbol Boundary Alignment (Word Alignment)

Because serial data streams have no natural packet markers, the receiver must establish where each 10-bit symbol starts and ends.

During the blanking interval (when no active image data is sent), the transmitter sends specific 10-bit control characters representing synchronization signals (HSync and VSync). These control symbols are distinct, transition-rich patterns:

  • 0010101011
  • 1101010100
  • 0001010101
  • 1110101010

A barrel shifter or framing logic monitors the incoming parallel data for these exact sequences. Once detected, the receiver locks its word boundaries to these patterns, ensuring every subsequent 10-bit capture corresponds to an aligned TMDS symbol.

Step 3: Differentiating Control Tokens from Video Data

Each 10-bit TMDS word represents either a 2-bit control signal (HSync, VSync, or data island preambles) or an 8-bit active video byte.

The receiver compares the received word against the four standardized control tokens. If a match is found, the receiver outputs the corresponding control signals and suppresses pixel output. If the word does not match any control token, it is routed to the color decoding logic as active video data.

Step 4: Reversing the 10-bit TMDS Encoding

Active video symbols consist of 10 bits, indexed here as \(S[9:0]\).

  • \(S[9]\) is the DC-balancing inversion flag.
  • \(S[8]\) indicates whether XOR or XNOR logic was used to minimize transitions.
  • \(S[7:0]\) are the encoded data bits.

Decoding reverses the encoding stages in strict reverse order:

1. Reversing DC Balancing (Bit 9)

The encoder sets \(S[9] = 1\) if it inverted the data bits to maintain DC balance across the transmission line. The receiver checks bit 9:

  • If \(S[9] == 1\), the receiver inverts the lower eight bits (\(S[7:0]\)) using a bitwise NOT operation.
  • If \(S[9] == 0\), the lower eight bits (\(S[7:0]\)) remain untouched.

Let the resulting 8-bit intermediate value be \(Q[7:0]\).

2. Reversing Transition Minimization (Bit 8)

Bit 8 identifies whether the original byte was encoded using XOR (\(S[8] = 1\)) or XNOR (\(S[8] = 0\)) operations. The original least significant bit was never modified, meaning the decoded bit \(D[0] = Q[0]\).

The remaining bits \(D[1]\) through \(D[7]\) are derived iteratively using the adjacent intermediate bits:

  • If \(S[8] == 1\) (XOR mode): \[D[i] = Q[i] \oplus Q[i-1]\] (The current decoded bit equals the current intermediate bit XORed with the preceding intermediate bit).

  • If \(S[8] == 0\) (XNOR mode): \[D[i] = \overline{Q[i] \oplus Q[i-1]}\] (The current decoded bit equals the current intermediate bit XNORed with the preceding intermediate bit).

Because these operations rely only on the received bits \(Q[i]\) and \(Q[i-1]\), all 8 bits can be calculated simultaneously in parallel hardware using combinational logic gates.

Step 5: Output Registering

The resulting 8-bit reconstructed value, \(D[7:0]\), represents the raw color intensity for that specific channel. The receiver aggregates the decoded 8-bit bytes from all three data channels simultaneously (Channel 0 for Blue, Channel 1 for Green, Channel 2 for Red), yielding a complete 24-bit RGB pixel per clock cycle for presentation to the display controller.