How Dual-Link DVI Splits Pixel Data

Dual-link DVI increases display bandwidth by utilizing two physical transmission channels to carry a single high-resolution digital video stream. This article explains the mechanism dual-link DVI uses to divide pixel data across its two links, detailing the spatial distribution scheme, the shared clock architecture, and how receiving hardware reconstructs the final image.

A standard Single-Link DVI connection employs Transition-Minimized Differential Signaling (TMDS) across four twisted pairs: three pairs dedicated to primary color channels (Red, Green, Blue) and one pair dedicated to the pixel clock. This configuration is capped at a 165 MHz pixel clock, providing enough bandwidth for resolutions up to 1920×1200 at 60 Hz.

Dual-Link DVI expands this interface by adding three more TMDS data pairs—providing a second RGB data path—while retaining the single original clock pair. In total, a dual-link connection utilizes six data channels and one shared clock channel.

The Alternating Pixel Mechanism

Dual-link DVI divides video data between the two links using a horizontal spatial split rather than splitting color components or alternating entire frames. The pixel stream is divided sequentially along each horizontal scanline:

  • Link 1 (Primary Link): Transmits all odd-numbered pixels in a scanline (Pixel 1, Pixel 3, Pixel 5, etc.).
  • Link 2 (Secondary Link): Transmits all even-numbered pixels in a scanline (Pixel 2, Pixel 4, Pixel 6, etc.).

Each link carries the complete 24-bit color data (8 bits each of red, green, and blue) for its assigned pixel. Because the color data is intact per pixel, neither link suffers from chroma subsampling or color channel degradation.

Clock Distribution and Synchronization

Although dual-link DVI doubles the data lines, it does not add a second clock channel. Both links run off the same single TMDS clock pair.

Because the pixels alternate between Link 1 and Link 2, each link transmits data at half the total pixel rate of the display. For example, if a 2560×1600 resolution display requires a composite pixel clock of 268 MHz, each individual link operates at 134 MHz. The single shared clock line carries this halved frequency, ensuring that both data streams remain inherently phase-aligned and synchronized from the transmitter to the receiver.

Blanking intervals (horizontal and vertical blanking) are handled consistently across both links. During blanking, both links transmit synchronization pulses (HSync and VSync) and control data tokens simultaneously so the display receiver tracks framing without drift.

Reassembly at the Display

Once the signals reach the display's internal scaler or timing controller (T-CON), the TMDS receiver decodes the two parallel data streams. The controller alternates reading from Link 1 and Link 2 to interleave the pixels back into the correct spatial order (1, 2, 3, 4, 5, 6...) inside a line buffer before writing the full horizontal line to the panel.

If a dual-link connection detects a display resolution that does not exceed the single-link threshold (165 MHz), the transmitter automatically deactivates Link 2. In this fallback state, Link 1 carries all consecutive pixels (odd and even) at the full standard clock rate.