How DisplayPort DP++ Interoperates with DVI

DisplayPort Dual-Mode, commonly designated as DP++, allows a DisplayPort source to directly drive single-link DVI displays using a simple, low-cost passive adapter. Instead of requiring an active protocol converter, a DP++ enabled graphics output detects the passive DVI adapter, changes its internal transmission mode from native DisplayPort packetized signals to Transition-Minimized Differential Signaling (TMDS), and remaps its physical pins to transmit DVI-compliant video and control signals.

Detection via the Cable Adapter Detect Pin

The interoperability process begins at the physical connection layer. In standard DisplayPort operation, Pin 13 acts as a configuration pin (Config1). When an adapter is connected, the DP++ source checks the electrical state of Pin 13, known in this context as the Cable Adapter Detect (CAD) pin.

A passive DP++ to DVI adapter pulls Pin 13 to ground or pulls it low through a specific resistor. When the graphics processing unit (GPU) senses this low logic state, it identifies that a DVI (or HDMI) passive adapter is attached rather than a native DisplayPort sink, triggering the source to switch into TMDS mode.

TMDS Mode and Pin Remapping

Native DisplayPort uses an AC-coupled, micro-packet architecture, whereas DVI relies on a DC-coupled, continuous streaming protocol called TMDS. When switched to dual-mode operation for single-link DVI, the source remaps its high-speed lanes and sideband channels:

  • Main Link Lanes 0, 1, and 2: The three primary differential data pairs used for DisplayPort data are reconfigured to carry TMDS Data Channels 0, 1, and 2 (transmitting the blue, green, and red color components).
  • Main Link Lane 3: In native DP mode, this lane carries data packets. Under DP++, it is remapped to transmit the continuous TMDS Clock signal required by DVI receivers.
  • AUX Channel to DDC: DisplayPort's bidirectional, differential Auxiliary (AUX) channel (Pins 5 and 7) is remapped to standard Display Data Channel (DDC) lines—I2C-based clock (SCL) and data (SDA) lines. This allows the source to read the monitor’s Extended Display Identification Data (EDID) and negotiate HDCP encryption.
  • Hot Plug Detect (HPD): Pin 18 continues to handle Hot Plug Detect signaling to notify the GPU when a monitor is attached or powered on.

Electrical Adaptation and Level Shifting

Although a DP++ GPU generates the TMDS logic protocol, its physical PHY outputs operate at lower DisplayPort voltages (typically around 0.4V to 1.2V peak-to-peak with AC coupling). Single-link DVI displays require standard 3.3V DC-coupled termination voltages.

Because of this difference, a passive DP++ to DVI adapter is not purely mechanical wire-routing; it contains a built-in level-shifter circuit. This simple hardware translates the source's low-voltage TMDS signals to the standard 3.3V signal levels expected by the DVI monitor, while also buffering the 3.3V DDC lines from the 5V pull-ups often found in DVI devices.

Bandwidth and Limitations

DP++ interoperability with single-link DVI adheres to the standard single-link DVI specification:

  • Clock Speed: The pixel clock is limited to a maximum of 165 MHz under the baseline Type 1 DP++ standard.
  • Resolution: This clock limit natively accommodates resolutions up to 1920x1200 at 60 Hz or 1080p.
  • Dual-Link Incompatibility: DP++ cannot drive dual-link DVI passively. Dual-link DVI requires six data channels plus a clock (seven differential pairs total), whereas DisplayPort connectors only route four high-speed differential pairs. Driving dual-link resolutions (such as 2560x1600) from any DisplayPort requires an externally powered, active adapter that converts the native DisplayPort stream into two multiplexed DVI links.