How CML Signaling Works in DVI TMDS Receivers

Current-Mode Logic (CML) serves as the physical signaling foundation for Transition Minimized Differential Signaling (TMDS) in DVI interfaces. Inside a DVI TMDS receiver, CML operates by terminating high-speed differential signal pairs through integrated pull-up resistors to a positive supply rail. As the transmitter switches constant current between the differential conductors, the receiver senses the resulting localized voltage drops, amplifies the differential threshold, and converts the analog current shifts back into digital logic states for clock and pixel recovery.

The Receiver Input Termination

The standard DVI TMDS receiver uses an internally biased, passive termination network. Each incoming differential pair—consisting of a non-inverting trace (\(IN+\)) and an inverting trace (\(IN-\))—is pulled up to the receiver's termination supply voltage (\(AV_{cc}\), typically +3.3V) through precision 50-ohm resistors.

Because the transmitter is an open-collector or open-drain differential pair that does not supply its own high-level driving voltage, the receiver itself provides the reference voltage and load for the entire signaling loop. The combination of matched 50-ohm line impedance and internal 50-ohm receiver termination creates a total 100-ohm differential impedance, minimizing high-frequency signal reflections along the transmission cable.

Current Steering and Voltage Translation

CML signaling functions by steering a constant current source (typically around 10 mA to 12 mA, defined by the transmitter) through one wire of the differential pair at a time:

  1. Logic State 1: The transmitter directs the nominal current down the \(IN-\) conductor to ground. The current flows from the receiver's \(AV_{cc}\) rail, through the internal 50-ohm termination resistor on \(IN-\), and across the cable. By Ohm's Law (\(V = I \times R\)), this induces a voltage drop of approximately 500 mV to 600 mV across that resistor, dropping the line voltage from 3.3V down to roughly 2.7V or 2.8V. Meanwhile, no current is drawn through the \(IN+\) line, keeping it pulled directly to \(AV_{cc}\) (3.3V).
  2. Logic State 0: The transmitter steers the current path to the \(IN+\) conductor instead. The \(IN+\) trace drops to roughly 2.7V, while the \(IN-\) trace returns to 3.3V.

The resulting differential swing is typically \(\pm 500\) mV to \(\pm 600\) mV, producing a peak-to-peak differential amplitude of 1.0V to 1.2V between the two traces.

Differential Amplification and Threshold Detection

Directly following the termination resistors, the receiver routes the two lines into a high-speed differential input comparator. Rather than measuring single-ended voltages relative to ground, the comparator measures the polarity and magnitude of the difference:

\[V_{diff} = V_{IN+} - V_{IN-}\]

When \(V_{diff}\) is positive, the comparator outputs an internal high logic state; when \(V_{diff}\) is negative, it outputs a low logic state.

Because the signaling relies on current steering referenced directly to the receiver's internal \(AV_{cc}\), the differential amplifier inherently cancels common-mode electromagnetic interference (EMI) and absorbs ground potential offsets between the source device and the display. High common-mode rejection allows the receiver to accurately interpret high-frequency data transitions exceeding 1.65 Gbps per channel without false triggering.

Data Recovery and Processing

Once the differential comparator resolves the low-voltage CML swings into internal rail-to-rail digital pulses (typically standard CMOS voltage levels), the signal passes into the receiver's clock and data recovery (CDR) circuitry:

  • Clock Extraction: A phase-locked loop (PLL) multiplies the incoming TMDS clock signal by a factor of 10 to establish a high-speed sampling clock synchronized with the serialized pixel data.
  • Deserialization: Shift registers sample the converted serial bitstream from the three primary TMDS data channels (carrying Red, Green, and Blue pixel components).
  • TMDS Decoding: The 10-bit encoded symbols are demultiplexed and decoded back into original 8-bit pixel values and display control signals (HSYNC, VSYNC, and data enable).