HSync and VSync Encoding in DVI TMDS Channel 0

The Digital Visual Interface (DVI) standard transmits video synchronization signals by mapping Horizontal Sync (HSync) and Vertical Sync (VSync) to TMDS Channel 0 during video blanking intervals. When active pixel transmission stops, the encoder switches from 8b/10b pixel data encoding to a 2-bit control encoding scheme. In this mode, HSync and VSync are assigned to the two control inputs of Channel 0, which are then converted into specialized 10-bit symbols designed for synchronization robustness and clock recovery.

The Role of the Data Enable (DE) Signal

A DVI transmitter operates in two primary states governed by the Data Enable (DE) signal:

  • Active Display Period (DE is High): The encoder processes 8-bit color components across three TMDS channels (Channel 0 for Blue, Channel 1 for Green, Channel 2 for Red). During this time, sync signals are not transmitted.
  • Blanking Interval (DE is Low): The active display area ends, and the blanking period begins. During this interval, pixel transmission is suspended, and the encoder ignores color data. Instead, it samples 2-bit control inputs (\(C0\) and \(C1\)) on each channel.

Control Signal Mapping on Channel 0

Each of the three TMDS data channels accepts two control bits (\(C0, C1\)) when DE is de-asserted. The DVI specification explicitly assigns the display synchronization signals to TMDS Channel 0:

  • \(C0\) carries the HSync (Horizontal Synchronization) signal.
  • \(C1\) carries the VSync (Vertical Synchronization) signal.

(Channels 1 and 2 also possess \(C0\) and \(C1\) inputs, but in baseline DVI, these are tied to binary 00 and reserved for future extensions or used in HDMI for packet headers).

The 10-Bit Control Token Encoding

When DE is low, the TMDS encoder bypasses the standard transition-minimization logic used for pixel data. Instead, it uses a fixed lookup table to convert the 2-bit \((C1, C0)\) combination into a predefined 10-bit symbol.

The mapping for \((C1, C0)\) to the 10-bit output (\(q_{out}[9:0]\)) is:

VSync (\(C1\)) HSync (\(C0\)) 10-bit TMDS Control Symbol (Binary) Hexadecimal
0 0 1101010100 0x354
0 1 0010101011 0x0AB
1 0 0101010100 0x154
1 1 1010101011 0x2AB

Purpose and Characteristics of Control Tokens

These specific 10-bit words were chosen intentionally for several physical-layer requirements:

  1. High Transition Density: Unlike active video data, which minimizes transitions to reduce electromagnetic interference (EMI), control tokens maximize transitions. Each 10-bit control pattern contains exactly seven signal transitions. This ensures the receiver's Phase-Locked Loop (PLL) maintains clock synchronization even during prolonged blanking periods.
  2. Uniqueness: None of the four 10-bit control codes overlap with the 460 possible 10-bit symbols used to represent active pixel data. This prevents the receiver from mistaking blanking intervals for image data and allows instant word-boundary alignment (framing).
  3. DC Balance: The four control symbols are balanced pairs. Transmitting alternating control states maintains DC neutrality across the differential transmission lines over time.

Receiver Decoding

When the DVI receiver decodes TMDS Channel 0:

  1. It detects the arrival of 10-bit control characters containing seven transitions, signaling the transition of DE to low.
  2. It uses these unique bit patterns to establish or verify 10-bit word framing.
  3. It directly maps the matched 10-bit symbol back to the corresponding 2-bit values, instantly reconstructing the original digital HSync and VSync waveforms for the display controller.