FPGA TMDS Synthesis to Drive a DVI Display

Field-Programmable Gate Arrays (FPGAs) can readily synthesize Transition Minimized Differential Signaling (TMDS) to drive DVI and HDMI displays without dedicated external transmitter chips. By leveraging native high-speed differential I/O standards, dedicated serializer blocks (SERDES), internal phase-locked loops (PLLs), and straightforward digital logic, modern FPGAs can generate the required 8b/10b encoded video streams directly. For low-cost FPGAs lacking native TMDS hardware support, external passive resistor networks can emulate the signaling levels to achieve reliable display output.

How TMDS and DVI Work

DVI video transport relies on TMDS, an electrical and logical standard comprising four differential pairs: three serial data channels (Red, Green, Blue) and one reference clock channel.

Logically, TMDS converts 8-bit color or control data into a 10-bit symbol. This 8b/10b encoding minimizes signal transitions to reduce electromagnetic interference (EMI) and maintains DC balance across the differential transmission lines.

Electrically, TMDS is a current-mode logic (CML) interface. The DVI display sink provides 50-ohm pull-up resistors to 3.3V on both lines of each differential pair. When transmitting, the source pulls one line low to create a nominal differential voltage swing between 400 mV and 600 mV.

Native FPGA Support

Most mid-range and modern low-cost FPGAs (such as AMD/Xilinx 7-Series, Lattice ECP5, and Intel Cyclone 10 LP) support direct TMDS output:

  • I/O Standards: Many FPGAs natively define a TMDS_33 I/O standard in their design suites. When configured, the I/O buffer matches the current-sinking characteristics needed by the display's 50-ohm pull-ups.
  • Serialization Hardware: A 10-bit parallel-to-serial conversion must occur for each TMDS channel. Dedicated blocks, such as Xilinx OSERDES or Lattice ODDRX1F, handle 10:1 or 5:1 double data rate (DDR) serialization directly at the I/O pin, avoiding timing closure issues inside the general routing fabric.
  • Clock Management: Generating TMDS requires a pixel clock (1x) and a high-speed bit clock (10x, or 5x using DDR). FPGA PLLs and mixed-mode clock managers (MMCMs) easily generate these phase-aligned clocks from a single reference oscillator.

Emulating TMDS on Budget FPGAs

Extremely low-cost FPGAs (such as the Lattice iCE40) may lack native TMDS or 3.3V differential output drivers. These chips can still drive DVI displays through two common workarounds:

  1. LVDS Drivers: If the FPGA supports Low-Voltage Differential Signaling (LVDS), an external AC-coupling network or series resistors can shift LVDS voltage swings to TMDS-compatible levels.
  2. Resistor DAC / Passive Attenuation: Standard 3.3V single-ended complementary CMOS outputs can drive the differential lines through a simple resistor network (typically 270-ohm series resistors on each line). This limits current draw and creates the proper voltage differential across the display's internal 50-ohm termination.

Core Internal Modules Required

Synthesizing a working DVI signal requires four core logic blocks within the FPGA fabric:

  1. Video Timing Generator: A counter-based state machine that generates horizontal and vertical sync pulses (hsync, vsync), active video blanking intervals, and pixel coordinates (\(X, Y\)).
  2. Pixel Generator: The logic or frame buffer memory that assigns color values (RGB 8:8:8) to active coordinates.
  3. TMDS Encoders: Three parallel logic blocks executing the standard DVI transition minimization algorithm and running at the 1x pixel clock.
  4. 10:1 Serializers: Three data serializers and one clock output buffer converting parallel data into serial bitstreams driven by the high-speed clock.

Resolution and Bandwidth Limits

The primary constraint when synthesizing TMDS inside an FPGA is the maximum operating frequency of the I/O pins and serializers:

  • Standard Definition / 640x480 @ 60Hz: Requires a 25.175 MHz pixel clock and a 251.75 Mbps data rate per channel. Almost any modern FPGA can handle this frequency with minimal routing constraints.
  • 720p / 1280x720 @ 60Hz: Requires a 74.25 MHz pixel clock and a 742.5 Mbps data rate. This falls comfortably within the capabilities of devices with dedicated SERDES primitives.
  • 1080p / 1920x1080 @ 60Hz: Requires a 148.5 MHz pixel clock and a 1.485 Gbps data rate. Achieving this rate typically requires higher-speed-grade FPGAs or devices equipped with multi-gigabit transceivers (such as GTX/GTP blocks).