DVI TMDS Control Tokens During Blanking Intervals

During the horizontal and vertical blanking intervals of a Digital Visual Interface (DVI) connection, no active pixel data is transmitted. Instead, Transition Minimized Differential Signaling (TMDS) data channels carry synchronization signals and control data formatted into specialized 10-bit control tokens. This article details the specific control signals assigned to each TMDS channel, the exact 10-bit token encodings used during blanking, and their role in maintaining receiver synchronization.

Channel Allocation of Control Signals

A standard single-link DVI connection consists of three TMDS data channels (Channel 0, Channel 1, and Channel 2) and one dedicated clock channel. During blanking intervals, each data channel is responsible for transmitting two distinct control bits (\(C0\) and \(C1\)) per TMDS clock cycle:

• Channel 0: Carries horizontal synchronization (HSYNC on \(C0\)) and vertical synchronization (VSYNC on \(C1\)).
• Channel 1: Carries control signals \(CTL0\) (on \(C0\)) and \(CTL1\) (on \(C1\)).
• Channel 2: Carries control signals \(CTL2\) (on \(C0\)) and \(CTL3\) (on \(C1\)).

In standard DVI implementations, \(CTL0\) through \(CTL3\) are typically reserved or held at logical zero, while Channel 0 actively transmits display timing via HSYNC and VSYNC.

2-Bit to 10-Bit Token Encoding

During active display time, 8-bit color data is converted into 10-bit transition-minimized characters. During blanking, however, the 2-bit control values (\(C1, C0\)) on each channel are mapped directly to pre-defined 10-bit control tokens.

The DVI 1.0 specification defines the mapping as follows:

(Note: Transmissions are serialized Least Significant Bit first, starting with bit 0).

Purpose and Characteristics of Control Tokens

These four tokens are engineered with specific properties essential for maintaining link stability:

1. Transition Maximization: Unlike video data, which uses transition minimization to reduce electromagnetic interference (EMI), control tokens maximize bit transitions (each token contains seven transitions). This high frequency of transitions allows the receiver's Phase-Locked Loop (PLL) to retain robust clock and phase synchronization during the non-active display period.
2. DC Balance: The tokens maintain near-constant DC balance, ensuring that differential signal lines do not suffer from baseline wander.
3. Word Alignment: The unique bit sequences of these four control tokens cannot occur anywhere in the transition-minimized active video data stream. The receiver uses these unmistakable patterns to establish and maintain 10-bit character boundary alignment (word framing).