DVI I2C DDC Pull-Up Resistor Values

This article covers the standard pull-up resistor values used for the I2C Display Data Channel (DDC) lines in Digital Visual Interface (DVI) designs. It explains the typical resistor ranges specified by video standards, where these resistors should be placed, and the electrical constraints—such as bus capacitance and drive strength—that dictate their values.

Standard Pull-Up Resistor Values

In DVI interfaces, the DDC lines (DDC Clock / SCL on pin 6 and DDC Data / SDA on pin 7) typically use pull-up resistors valued between 1.5 kΩ and 2.2 kΩ.

While general-purpose I2C buses operating at standard mode (100 kHz) frequently use 4.7 kΩ or 10 kΩ resistors, DVI applications require stronger (lower resistance) pull-ups. The most common standard recommendation across VESA and DVI transmitter application notes is 1.5 kΩ to 2.0 kΩ.

Voltage Rail

The DDC pull-up resistors must be tied to the +5V power rail (provided on Pin 14 of the DVI connector). Although modern graphics processors and microcontrollers operate at 3.3V or lower, the DVI and VESA E-DDC specifications dictate a 5V signaling environment to maintain backward compatibility with standard 5V EDID EEPROMs (such as the 24C02). Level shifters or open-drain buffers tolerant to 5V are standardly employed between the low-voltage host controller and the DDC lines.

Source vs. Sink Placement

  • Source (Transmitter/Graphics Card): The primary pull-up resistors (1.5 kΩ to 2.2 kΩ) must reside on the source device. The source supplies the +5V power signal to the cable and pulls the SCL and SDA lines high.
  • Sink (Receiver/Monitor): The sink device typically contains only the EDID EEPROM. Sinks generally do not include low-impedance pull-ups to prevent back-powering or parallel resistance drops. If a sink does include pull-ups, they are very weak (typically 47 kΩ or higher) to avoid pulling down the effective bus resistance when connected to the host.

Engineering Considerations for Resistor Selection

Choosing the correct value within the 1.5 kΩ to 2.2 kΩ range depends on two main electrical factors:

  • Bus Capacitance and Rise Time: DVI cables can be several meters long, introducing significant parasitic capacitance (often approaching or exceeding the standard I2C limit of 400 pF). According to the I2C standard-mode specification, maximum allowable signal rise time (\(t_r\)) is 1000 ns. Lower pull-up values (such as 1.5 kΩ) provide the faster rise times necessary to overcome this cable capacitance.
  • Sink Current Capabilities (\(I_{OL}\)): Standard I2C devices are rated to sink a minimum of 3 mA while maintaining a low-level output voltage (\(V_{OL}\)) below 0.4V. Pulling up to 5V using a resistor smaller than 1.5 kΩ (\(5\text{V} / 1.5\text{ k}\Omega \approx 3.33\text{ mA}\)) risks exceeding the maximum current sink capability of standard EDID EEPROMs, which can prevent the lines from being pulled low enough to register a valid logic-zero state.