Dual-Link DVI Pixel Interleaving Explained

Dual-link Digital Visual Interface (DVI) expands the video bandwidth of standard single-link connections to accommodate higher resolutions and refresh rates by doubling the number of Transition-Minimized Differential Signaling (TMDS) data pairs from three to six. Instead of splitting an image spatially or sending alternating frames, dual-link DVI operates by interleaving adjacent horizontal pixels across the two physical links in real time. This article details the hardware architecture, transmission mechanics, and receiver reconstruction methods that allow dual-link DVI to distribute odd and even pixels across its data channels.

Channel Architecture and Mapping

Standard single-link DVI relies on four twisted-pair copper conductors: three TMDS data channels (carrying red, green, and blue color information) and one TMDS clock channel. Dual-link DVI adds three additional data channels while retaining the single, shared TMDS clock channel.

The six data channels are organized into two distinct physical links:

  • Link 1 (Primary Link): Comprises Channel 0 (Blue + HSync/VSync), Channel 1 (Green), and Channel 2 (Red).
  • Link 2 (Secondary Link): Comprises Channel 3 (Blue), Channel 4 (Green), and Channel 5 (Red).

Both links operate synchronously using the single clock pair, ensuring precise phase alignment without requiring a separate clock signal for the secondary connection.

The Interleaving Process

Pixel interleaving occurs along the horizontal raster scan line. As the graphics processing unit (GPU) processes pixels from left to right across a display line, it alternates the assignment of each pixel to Link 1 or Link 2:

  1. First Pixel (Odd): The first pixel of a scan line (Pixel 0 in zero-indexed notation, or Pixel 1 in standard counting) is encoded into 10-bit TMDS characters and dispatched simultaneously across Channels 0, 1, and 2 on Link 1.
  2. Second Pixel (Even): The adjacent pixel immediately to the right is encoded and transmitted concurrently across Channels 3, 4, and 5 on Link 2.
  3. Subsequent Pixels: The transmitter continues this alternating pattern across the entire active horizontal scan line. All odd-numbered pixels travel through Link 1, while all even-numbered pixels travel through Link 2.

Because transmission occurs in parallel, two full 24-bit pixels (one odd, one even) are transmitted across the cable during a single TMDS clock cycle.

TMDS Clocking and Timing Dynamics

Because two pixels are transmitted simultaneously, the shared TMDS clock runs at half the effective pixel clock rate of the display mode. For example, rendering a resolution that demands a 268 MHz pixel clock requires the physical TMDS clock line to operate at only 134 MHz.

During horizontal and vertical blanking intervals, control signals—including horizontal sync (HSync) and vertical sync (VSync)—are transmitted exclusively over Link 1 (Channel 0). Link 2 does not carry synchronization pulses during blanking, which avoids timing discrepancies and reduces electrical crosstalk across the connector pins.

Receiver Reconstruction

At the receiving end (the monitor or scalar board), the hardware performs the reverse operation:

  1. The receiver recovers the shared clock and samples all six differential data pairs concurrently.
  2. The incoming 10-bit TMDS characters are decoded back into their original 8-bit RGB color components for both links simultaneously.
  3. The display controller alternates between the Link 1 buffer and the Link 2 buffer to place the pixels back into their sequential horizontal order (Odd, Even, Odd, Even).
  4. The reconstructed stream is output to the internal timing controller (T-CON) as a single, coherent, high-bandwidth pixel pipeline for panel driving.