Does Dual-Link DVI Use One or Two Clock Pairs?

Dual-link DVI is designed to double the video bandwidth of standard single-link connections to support higher resolutions and refresh rates. While it doubles the amount of data channels available for image transmission, it does not duplicate every connection. Specifically, dual-link DVI utilizes a single shared clock pair rather than two independent clock pairs, using that single reference signal to synchronize all data lanes simultaneously.

A standard Single-Link DVI connection relies on Transition Minimized Differential Signaling (TMDS) and consists of four differential pairs:

  • Three data pairs (TMDS Data 0, 1, and 2) carrying the red, green, and blue color channels.
  • One clock pair (TMDS Clock) providing the frequency reference for the data channels.

To handle higher bandwidth demands—such as 2560×1600 at 60 Hz—Dual-Link DVI expands the interface. It adds three more data pairs (TMDS Data 3, 4, and 5) to the cable, providing a total of six data channels. Despite this increase in data capacity, the specification does not add a second clock channel. Both Link 1 and Link 2 share the original TMDS clock pair.

  1. Pixel Synchronization and Skew Prevention: In dual-link mode, the transmitter alternates pixel transmission between the two links—typically sending odd-numbered pixels across Link 1 and even-numbered pixels across Link 2. Using a single, shared clock ensures that both data streams remain strictly synchronized in phase and frequency, avoiding skew and jitter issues that could occur if two separate clock generators were drifting independently.
  2. Connector Pin Limitations: Standard DVI connectors feature 24 digital pins arranged in a 3×8 grid. Adding a second clock channel would require an extra differential pair (two signal pins plus a dedicated shield pin), which would exceed the standard pinout format of the DVI specification.

Operating Frequency Across the Shared Clock

When a display operates within single-link limits (up to a 165 MHz pixel clock), only Link 1 is active. When the required pixel rate exceeds 165 MHz, the transmitter switches to dual-link mode. Because the pixel data is split evenly between the six data channels, the frequency carried over the shared clock pair runs at half the total pixel rate, allowing the interface to transmit high-resolution video reliably without exceeding the physical signal limits of the cable.