Adapting DP++ to DVI: Voltage Level Shifting

Adapting DisplayPort Dual-Mode (DP++) to Digital Visual Interface (DVI) requires active electrical translation, primarily consisting of shifting low-voltage AC-coupled data signals to standard 3.3V DC-coupled Current Mode Logic (CML) and converting 3.3V Display Data Channel (DDC) logic to 5V. While DP++ allows the source GPU to output Transition-Minimized Differential Signaling (TMDS) protocols, the physical interface operates at lower voltages than native DVI, necessitating hardware level shifters within the adapter cable.

TMDS Differential Lane Level Shifting

Native DisplayPort interfaces operate using low-voltage, AC-coupled differential signaling with typical swings between 400 mV and 1200 mV. When operating in DP++ mode, the source GPU outputs TMDS-encoded data (three data pairs and one clock pair) across the main link pins, but maintains low-voltage electrical characteristics incompatible with direct DVI inputs.

  • DVI TMDS Requirements: Standard DVI utilizes DC-coupled Current Mode Logic (CML). The receiver terminates each differential line to a +3.3V rail through 50-ohm pull-up resistors, yielding a nominal common-mode voltage near 3.3V with a differential voltage swing between 400 mV and 600 mV.
  • The Voltage Shift: The level-shifting circuit inside the DP++ to DVI adapter removes the AC coupling and shifts the DP++ low-voltage differential signals to the 3.3V CML domain required by the DVI receiver.

DDC and HPD Line Voltage Conversion

Communication between the graphics card and the monitor for Extended Display Identification Data (EDID) and Hot Plug Detect (HPD) uses different logic levels across both standards:

  • I2C / DDC Lines (SDA and SCL): DP++ repurposes the DisplayPort Auxiliary (AUX) channel into a bidirectional I2C bus for DDC communication, operating at 3.3V logic levels. DVI specifications mandate a 5V I2C bus. Consequently, the adapter must implement bidirectional voltage level shifting between 3.3V and 5.0V for the clock and data lines.
  • Hot Plug Detect (HPD): The DVI monitor asserts an HPD signal up to 5V when connected. DisplayPort controllers accept a maximum of 3.3V on the HPD pin. The adapter must attenuate or shift this 5V signal down to 3.3V to prevent damaging the source GPU.

Power Rail Conversion (3.3V to 5V)

DisplayPort provides power to adapters via Pin 20 (DP_PWR) at +3.3V DC (up to 500 mA). Standard DVI requires a dedicated +5V supply line on Pin 14 to power the monitor's EDID EEPROM during power-saving states.

A passive DP++ to DVI adapter includes an internal DC-to-DC boost converter or charge pump that steps the incoming 3.3V from the DP source up to 5V to power both the DVI +5V rail and the 5V pull-up resistors for the DDC lines.