Active Equalizer Circuits in High-End DVI Repeaters

High-end DVI repeaters rely on specialized active equalizer circuits to restore degraded Transition-Minimized Differential Signaling (TMDS) streams over long copper cables. By countering high-frequency attenuation, phase jitter, and inter-symbol interference (ISI), these circuits reconstruct the digital signal to maintain display integrity at high resolutions. The primary active equalization stages deployed in professional-grade DVI hardware include Continuous-Time Linear Equalizers (CTLE), Decision Feedback Equalizers (DFE), limiting amplifiers, and Phase-Locked Loop (PLL)-based retiming architectures.

Continuous-Time Linear Equalizers (CTLE)

The first line of defense in an active DVI repeater is the Continuous-Time Linear Equalizer. Long DVI cables act as low-pass filters due to skin effect and dielectric losses, causing the high-frequency components of TMDS signals to attenuate much faster than the low-frequency components.

A CTLE circuit is an analog active filter that applies an inverse frequency response to that of the cable. Utilizing differential pairs with capacitive and resistive source-degeneration, the CTLE provides high-frequency peaking while keeping low-frequency gain flat. This effectively opens closed "data eyes" before the signal reaches sampling stages. In high-end repeaters, CTLE stages are often adaptive, measuring incoming signal transitions and automatically tuning RC feedback networks to match the specific length and gauge of the attached DVI cable.

Decision Feedback Equalization (DFE)

While CTLE combats channel loss, it also amplifies high-frequency crosstalk and noise. To overcome this limitation, high-end repeaters incorporate Decision Feedback Equalizers.

A DFE is a non-linear equalizer that uses previous bit decisions to synthesize and subtract post-cursor ISI from the current incoming bit. Because the feedback loop uses resolved digital values rather than raw analog voltages, the DFE removes severe reflections and multi-path distortions without amplifying broadband channel noise. A typical DFE implementation in a DVI receiver features between 2 to 5 taps, allowing the circuit to cancel interference spanning multiple unit intervals (UI).

Limiting Amplifiers and Differential Slicers

Following linear filtering and ISI cancellation, the recovered analog waveform passes into a multi-stage differential limiting amplifier, commonly referred to as a slicer.

This circuit consists of high-gain, wide-bandwidth differential gain stages configured to saturate quickly. The slicer converts the equalized, low-amplitude differential analog signals back into full-amplitude, sharp digital square waves compatible with standard TMDS logic levels. Built-in hysteresis prevents false switching caused by baseline wander and residual high-frequency ripple.

PLL-Based Clock and Data Recovery (CDR) Retimers

Basic repeaters (redrivers) only restore amplitude using CTLE and limiting amplifiers, leaving accumulated jitter intact. High-end repeaters function as active retimers, integrating dedicated Clock and Data Recovery (CDR) circuits powered by low-jitter Phase-Locked Loops (PLLs).

The DVI interface transmits a dedicated TMDS clock alongside three data lanes. In high-end repeaters, a primary PLL multiplies the TMDS clock to generate sampling clocks aligned with the data transmission rate (10x the pixel clock). A phase interpolator or individual CDR loop per data lane tracks phase variations, re-sampling the equalized data precisely in the center of the restored eye diagram. This completely decouples jitter accumulated from the cable source, driving pristine, newly synthesized TMDS signals with exceptionally low jitter down the next cable segment.