Why DisplayPort 2.0 Switched to 128b/132b Encoding

When the Video Electronics Standards Association (VESA) introduced DisplayPort 2.0, the most critical architectural upgrade was the transition from legacy 8b/10b line encoding to a modern 128b/132b scheme. This article explores why VESA made this transition, focusing on the dramatic reduction in transmission overhead, the massive increase in usable payload bandwidth required for modern high-resolution displays, and the technological alignment with the USB4 standard.

Drastic Reduction in Protocol Overhead

Older standards from DisplayPort 1.0 through DisplayPort 1.4a utilized 8b/10b encoding. In an 8b/10b system, every 8 bits of actual data require a 10-bit physical transmission symbol to ensure clock recovery and maintain direct current (DC) balance across the physical link. This 2-bit addition created a massive 20% protocol overhead. Consequently, while DisplayPort 1.4 offered a raw maximum physical link rate of 32.4 Gbps, it yielded only 25.92 Gbps of usable payload throughput.

By contrast, the 128b/132b encoding introduced in DisplayPort 2.0 adds only 4 framing bits for every 128 bits of payload data. This drastically slashes the protocol overhead from 20% down to approximately 3.125%, resulting in a transmission efficiency of nearly 97%.

Unlocking Bandwidth for Next-Generation Displays

The primary driver for reducing overhead was the immense data requirement of next-generation display setups. DisplayPort 2.0 introduced three Ultra-High Bit Rate (UHBR) transmission tiers: UHBR 10, UHBR 13.5, and UHBR 20.

Under the top-tier UHBR 20 specification across four physical lanes, the link achieves an 80 Gbps raw bit rate. Thanks to the 96.875% efficiency of 128b/132b encoding, the interface delivers up to 77.37 Gbps of usable payload bandwidth—almost triple the real-world performance of DisplayPort 1.4. This throughput enables single-cable capabilities that were previously impossible without extreme compression or compromise, such as:

• Driving uncompressed 8K displays at 60Hz with 10-bit HDR (4:4:4).
• Supporting dual 4K displays at 144Hz without compression.
• Outputting up to 16K resolution at 60Hz when combined with Display Stream Compression (DSC).

Physical Layer Synergy with USB4 and USB Type-C

The shift to 128b/132b was also driven by convergence with the USB ecosystem. DisplayPort 2.0 was developed in close coordination with the USB Implementers Forum (USB-IF) to ensure seamless operation over the USB Type-C connector and native support for tunneling inside the USB4 protocol architecture.

USB4 and modern PCI Express architectures already leverage high-efficiency, block-based encoding standards (such as 128b/130b and 128b/132b) paired with sophisticated scrambling algorithms to maintain DC balance and signal integrity without bloating overhead. By adopting 128b/132b, VESA ensured that the physical layer (PHY) and transceiver hardware designs could be shared or easily adapted across both USB4 and DisplayPort controllers, lowering manufacturing costs and improving signal reliability at extreme frequencies.