SerDes PLL Implementation for DisplayPort Clocks

Serializer/Deserializer (SerDes) architectures in DisplayPort systems rely on specialized Phase-Locked Loops (PLLs) to generate, synchronize, and recover high-speed serial clocks. Because DisplayPort embeds the clock directly into the transmitted data stream rather than using a dedicated clock line, SerDes designs deploy transmit (TX) PLLs to synthesize multi-gigahertz clocks from a low-frequency reference, and receive (RX) Clock and Data Recovery (CDR) PLLs to reconstruct the clock at the sink. This implementation must simultaneously accommodate variable link rates, handle down-spread spectrum clocking for electromagnetic interference (EMI) reduction, and maintain strict jitter budgets required by modern standards from RBR up to UHBR20.

Transmitter (TX) PLL Architecture

The TX SerDes uses a PLL to multiply a low-frequency reference clock (typically 27 MHz, 100 MHz, or 135 MHz) up to the target bit rate's fundamental frequency.

  1. VCO Topologies: DisplayPort implementations typically choose between Ring Oscillators and LC Tank Voltage-Controlled Oscillators (LC-VCOs). Ring oscillators offer a compact silicon footprint and wide tuning ranges, making them suitable for lower DisplayPort speeds (RBR, HBR). High Bit Rate 2 (HBR2), HBR3, and Ultra High Bit Rate (UHBR) modes generally mandate LC-VCOs due to their superior phase noise performance and lower intrinsic jitter, which are necessary to meet strict eye-diagram masks at speeds up to 20 Gbps per lane.
  2. Frequency Synthesis and Dividers: A programmable feedback divider network scales the VCO output. Modern designs employ Fractional-N PLL architectures with delta-sigma (\(\Delta\Sigma\)) modulators to achieve fine frequency resolution, allowing the SerDes to toggle seamlessly between standard link rates (1.62, 2.7, 5.4, 8.1, 10, 13.5, and 20 Gbps) using a single reference oscillator. Post-VCO dividers generate multi-phase clocks (e.g., quadrature 0°, 90°, 180°, 270°) used to drive half-rate or quarter-rate serializer topologies.

Spread-Spectrum Clocking (SSC) Support

DisplayPort mandates the use of down-spread spectrum clocking (typically 0% to -0.5% modulation at a 30 kHz to 33 kHz rate) to reduce peak EMI emissions.

TX PLLs implement this modulation directly in the clock generation stage. Rather than modulating the input reference clock externally, modern SerDes TX PLLs inject digital modulation profiles directly into the feedback divider using a \(\Delta\Sigma\) fractional controller. The loop bandwidth of the TX PLL must be designed wide enough to track this 30–33 kHz modulation profile accurately without distorting the modulation shape or introducing excessive phase jitter.

Receiver (RX) Clock and Data Recovery (CDR)

At the sink device, the RX SerDes implements a PLL-based CDR system to extract the timing information directly from the transitions of the incoming 8b/10b (DP 1.4) or 128b/132b (DP 2.0/2.1) encoded data.

  1. Dual-Loop CDR Architecture: DisplayPort RX architectures frequently use a dual-loop topology consisting of a frequency acquisition loop and a phase acquisition loop. The frequency loop coarse-tunes the internal oscillator to match the nominal standard link rate, while the phase loop uses a Phase Detector (such as an Alexander or Hogge phase detector) to align the sampling clock phase to the center of the received data eye.
  2. Phase Interpolator (PI) Based CDR: To save area and power in multi-lane configurations (up to 4 lanes per DisplayPort interface), many modern SerDes implementations share a single centralized PLL that feeds high-speed clock phases to all lanes. Each lane features an independent Phase Interpolator (PI) driven by a digital loop filter. The PI continuously shifts the phase of the central clock to track lane-specific skew, high-frequency jitter, and the common SSC profile.

Jitter Filtering and Loop Bandwidth Requirements

DisplayPort compliance standards define strict jitter transfer and jitter tolerance masks:

  • TX PLL Jitter Transfer: The TX PLL loop filter acts as a low-pass filter to reference clock phase noise while attenuating high-frequency noise generated by internal components. The loop bandwidth is tuned high enough to track the required SSC profile but low enough to reject high-frequency reference clock jitter.
  • RX CDR Jitter Tolerance: The RX CDR PLL acts as a high-pass filter to input jitter. It must possess a sufficiently wide tracking bandwidth (typically in the megahertz range) to track and absorb low-frequency jitter, baseline wander, and the 30–33 kHz SSC profile without misinterpreting data bits. High-frequency jitter that falls outside the CDR tracking bandwidth is absorbed by the timing margin of the receiver's equalization circuitry (CTLE and DFE).