How DisplayPort Reconstructs the Pixel Clock

Unlike legacy video interfaces that transmit a dedicated pixel clock along with the video data, DisplayPort decouples the pixel rate from the physical link transmission rate. The receiver reconstructs the original pixel clock by first extracting a high-speed link symbol clock from the serial data stream via Clock and Data Recovery (CDR), and then using mathematical frequency synthesis driven by time-stamp parameters—known as the M and N values—transmitted in the stream's metadata.

The Decoupled Architecture

DisplayPort transmits packetized data across a fixed-rate Main Link (such as 1.62 Gbps for RBR, 2.7 Gbps for HBR, or 5.4 Gbps for HBR2). Because the native pixel clock frequency of the source video rarely matches these fixed link symbol rates, the source cannot directly clock the transmission. Instead, the pixel data is packed into micro-packets, leaving the receiver responsible for regenerating the exact timing required to drive the display panel.

Before regenerating the pixel clock, the receiver must extract the link symbol clock from the incoming serial bitstream. DisplayPort uses line coding (such as 8b/10b in DP 1.4 or 128b/132b in DP 2.0/2.1) to guarantee frequent signal transitions.

The receiver's Clock and Data Recovery (CDR) circuitry locks onto these transitions using an internal Phase-Locked Loop (PLL). Once locked, the CDR produces a synchronized bit clock, which is then divided down to produce the link symbol clock (\(f_{LS\_CLK}\)).

Step 2: Extracting the M and N Values

To communicate the relationship between the link symbol clock and the original pixel clock, the source generates two integer values:

  • \(M_{vid}\) (Video M): A dynamic counter tracking the number of pixel clock cycles.
  • \(N_{vid}\) (Video N): A reference counter tracking the link symbol clock cycles (often configured to a fixed power of two, such as \(2^{15} = 32,768\) or \(2^{16} = 65,536\)).

The source inserts these values into the Main Stream Attribute (MSA) packets during the vertical and horizontal blanking intervals of the stream.

Step 3: Frequency Synthesis via Phase-Locked Loop

The relationship between the pixel clock frequency (\(f_{pixel}\)) and the link symbol clock frequency (\(f_{LS\_CLK}\)) is governed by the following ratio:

\[f_{pixel} = f_{LS\_CLK} \times \frac{M_{vid}}{N_{vid}}\]

The receiver feeds the extracted \(f_{LS\_CLK}\) along with the decoded \(M_{vid}\) and \(N_{vid}\) values into a fractional-N synthesizer or a specialized pixel PLL. In a typical hardware implementation:

  1. The link symbol clock is divided by \(N_{vid}\).
  2. The generated reference is multiplied by \(M_{vid}\).
  3. The PLL phase-detector compares the synthesized clock against the reference to drive a Voltage-Controlled Oscillator (VCO), producing a continuous, low-jitter pixel clock identical in frequency and phase to the source's original clock.

Handling Drift and Spread Spectrum Clocking (SSC)

In asynchronous clocking mode, or when Spread Spectrum Clocking (SSC) is enabled to reduce electromagnetic interference, the ratio between the pixel clock and link clock can shift over time.

DisplayPort handles this by allowing the source to continuously recalculate and transmit updated \(M_{vid}\) values in the MSA packets. The receiver's clock synthesis loop smoothly filters these variations, tracking any source drift or modulation without causing audio/video desynchronization or visual artifacts.