How DisplayPort Receivers Deskew Lane Data

DisplayPort interfaces transmit high-speed video and audio across up to four independent physical lanes, making inter-lane skew inevitable due to differences in trace lengths, packaging, and component variations. To present a unified, coherent data stream to the display processing engine, DisplayPort receivers implement dedicated deskew circuitry. This process relies on specialized link training patterns, per-lane Clock and Data Recovery (CDR), and elastic FIFO buffers that detect alignment markers and synchronously release data across all lanes.

The Source of Inter-Lane Skew

In high-speed differential signaling, trace length mismatches of even a fraction of a millimeter result in picoseconds of propagation delay. Printed circuit board (PCB) routing constraints, via transitions, connector pin assignments, and variations in PCB dielectric constants cause bits dispatched simultaneously by the transmitter (GPU) to arrive at the receiver (monitor) at different times. At modern DisplayPort transmission rates—ranging from 1.62 Gbps (RBR) to 20 Gbps (UHBR20) per lane—this delay can easily span multiple symbol periods, necessitating active compensation.

Phase 1: Clock and Data Recovery (CDR)

Deskewing cannot occur until the receiver properly captures the raw bits on each lane independently. Because DisplayPort embeds the clock within the data stream, the receiver routes each lane to its own dedicated CDR unit. During the initial phase of link training, the transmitter sends Training Pattern Sequence 1 (TPS1). The CDR lock loops onto the transitions in this pattern, locking the phase and frequency to generate a local sampling clock for each lane. Once locked, the receiver can reliably convert the continuous analog waveform into a discrete serial bit stream.

Phase 2: Symbol Lock and Framing

After achieving CDR lock, the receiver must establish symbol boundaries. For DisplayPort 1.4 and older standards using 8b/10b encoding, the receiver scans the serial stream for unique framing characters such as the K28.5 "Comma" symbol. In DisplayPort 2.1 utilizing 128b/132b channel encoding for Ultra High Bit Rate (UHBR) links, the receiver synchronizes to standardized 4-bit sync headers. Once the receiver detects these markers, it correctly groups the incoming bits into distinct symbols or blocks.

Phase 3: Alignment Detection via Training Patterns

To measure and eliminate skew across the active lanes, the transmitter switches to advanced training patterns—such as TPS2, TPS3, or TPS4. During this phase:

  1. The transmitter simultaneously transmits a predetermined alignment character across all active lanes at the exact same symbol period.
  2. The receiver receives these alignment characters at staggered intervals depending on the physical delay of each lane.
  3. A deskew controller monitors the parallel symbol outputs of each lane to detect the exact arrival time of these markers.

Phase 4: Elastic FIFO Buffer Deskewing

The actual deskewing mechanism is centered around a set of elastic First-In, First-Out (FIFO) buffers, with one FIFO assigned to each receiver lane.

  • Writing to the FIFOs: As each lane decodes its incoming symbols, it writes them into its respective FIFO using its individual recovered clock. The fastest lane will write the alignment marker into its FIFO first, while slower lanes write it cycles later.
  • Holding and Aligning: The deskew logic halts or delays reading from the FIFOs until the alignment symbol has safely arrived and been registered in the FIFOs of all active lanes.
  • Synchronous Reading: Once all lanes indicate the presence of the alignment symbol, the receiver adjusts the read pointers of each FIFO. The read pointers are configured so that reading the alignment symbol—and all subsequent data symbols—occurs simultaneously across all FIFOs on a single, shared internal clock domain.

Dynamic Skew Tolerance

DisplayPort standards mandate that receivers support a specific maximum lane-to-lane skew budget, typically accommodating several symbol times (tens of nanoseconds). The physical depth of the elastic buffers defines this tolerance window. As long as the physical routing skew stays within the limits defined by the DisplayPort specification, the elastic buffers absorb the delay disparities entirely, outputting fully aligned parallel data to the main link de-framing and pixel-generation stages.