How DisplayPort Maintains Constant Link Symbol Rates

DisplayPort operates using fixed physical link rates regardless of the resolution, color depth, or refresh rate of the transmitted video. Because the native pixel clock of a display rarely matches these fixed transmission speeds, DisplayPort bridges the bandwidth gap by inserting dummy data, known as stuffing or blanking symbols, directly into the stream. This article explains how the DisplayPort architecture decouples pixel and link clocks, uses Transfer Units to pad active video data, and leverages blanking intervals to ensure continuous synchronization across the physical lanes.

Traditional display interfaces like VGA and DVI run at a variable clock speed directly tied to the video source's pixel clock. DisplayPort, by contrast, operates at fixed physical symbol rates—such as 1.62 Gbps (RBR), 2.7 Gbps (HBR), 5.4 Gbps (HBR2), 8.1 Gbps (HBR3), or higher with UHBR standards.

Because the bandwidth of the physical link almost always exceeds the actual data rate of the incoming video stream, the source must reconstruct the pixel clock at the display end without altering the transmission speed. It accomplishes this by transmitting clock-regeneration parameters known as \(M_{VID}\) (video stream time-base count) and \(N_{VID}\) (link symbol clock count) inside Main Stream Attributes (MSA) packets.

Transfer Units and Active Data Stuffing

To regulate data throughput during active video lines, DisplayPort segments data into fixed-size containers called Transfer Units (TUs). A Transfer Unit typically consists of 32 to 64 link symbols per lane.

When the active pixel rate is lower than the total capacity of a TU:

  1. The transmitter sends active pixel symbols at the start of the TU.
  2. Once all valid pixel data for that interval is allocated, the transmitter inserts non-data stuffing symbols (dummy bytes) into the remainder of the TU.
  3. The receiver uses the known packing format and framing characters to strip away the stuffing symbols, buffering and replaying the actual video data at the reconstructed pixel clock frequency.

By dynamically adjusting the ratio of valid video symbols to stuffing symbols within each TU, the transmitter precisely matches the average data consumption rate to the video source without altering the underlying physical symbol clock.

Horizontal and Vertical Blanking Framing

In addition to active video stuffing, video signals require horizontal blanking (HBlank) and vertical blanking (VBlank) intervals between lines and frames. DisplayPort does not stop the high-speed serialized data clock during these intervals; instead, it sends framing characters and auxiliary information.

  • Blanking Start (BS): The transmitter emits a specialized control symbol (a K-code such as K28.5 in 8b/10b encoding, or an equivalent framing marker in 128b/132b encoding) that marks the transition from active video to the blanking period.
  • Vertical Blanking ID (VB-ID): Immediately following the BS symbol, the transmitter sends a VB-ID byte indicating whether the link is currently in a vertical blanking period, field identification for interlaced video, or audio mute states.
  • Dummy Symbols and Secondary Data: Throughout the blanking period, the transmitter sends dummy symbols to fill time, interspersed with secondary data packets such as audio streams, HDR metadata, or CEA information frames.
  • Blanking End (BE): When the blanking interval finishes and the next line of active video begins, the transmitter inserts a Blanking End symbol, notifying the receiver to resume pixel processing.

Physical Layer Continuity and Clock Recovery

The primary purpose of continuously sending stuffing symbols and blanking characters is to maintain physical layer stability. High-speed serial transceivers rely on Clock Data Recovery (CDR) circuits that extract the clock directly from transitions in the received data stream.

If transmission stopped during blanking intervals, the receiver's phase-locked loops (PLLs) would lose lock, resulting in signal degradation, resynchronization delays, and high jitter. By filling all idle periods with pseudo-randomly scrambled blanking and stuffing symbols, DisplayPort guarantees constant DC balance, provides regular transition density for CDR tracking, and maintains uninterrupted symbol rates across all active lanes.