How DisplayPort Handles Interlaced vs Progressive Video

The DisplayPort standard natively prioritizes progressive scan video while retaining backward compatibility for interlaced video formats through dedicated metadata signaling. While progressive scan renders every line of a frame sequentially in a single pass, interlaced formats split a frame into two alternating fields of odd and even lines. DisplayPort accommodates both approaches through its packet-based architecture, using Main Stream Attribute (MSA) data packets to inform the display sink whether the incoming pixel stream is progressive or interlaced, allowing modern digital displays to reconstruct or deinterlace the image accurately.

Native Progressive Scan Architecture

DisplayPort was designed primarily for modern flat-panel displays, such as LCDs and OLEDs, which are inherently progressive devices. In progressive scan mode (such as 1080p or 4K), the source device sends complete frames sequentially:

  • Frame Delivery: Every horizontal line of pixels is transmitted in order from the top-left to the bottom-right of the display during each refresh cycle.
  • Pixel Streaming: The DisplayPort transmitter packages these lines into micro-packets and streams them across the Main Link data lanes.
  • Direct Presentation: The display controller receives whole frames and updates every physical pixel row simultaneously, resulting in a cleaner image free of comb-like motion artifacts and eliminating the need for frame reconstruction.

Interlaced Video Handling and the Main Stream Attribute (MSA)

Interlaced video formats (such as 1080i or 480i) originated in analog television broadcasting to conserve transmission bandwidth. Because DisplayPort is a fully digital, packetized protocol, it does not use analog sweep timing. Instead, it handles interlaced content using digital field identification:

  • Field-Based Transmission: Rather than transmitting an entire frame at once, the source transmits one field at a time—first the odd lines (Field 1), followed by the even lines (Field 2).
  • Metadata Flags in MSA: During the vertical blanking interval, DisplayPort transmits Main Stream Attribute (MSA) packets. Within these packets, specific configuration bits (specifically located in the MISC0 register) signal the display sink:
    • A dedicated bit indicates whether the stream is progressive (0) or interlaced (1).
    • Additional flags define the field polarity, signaling whether the incoming field contains odd or even lines.
  • Vertical Timing Tracking: The vertical sync parameters in the MSA adjust dynamically between fields to account for the half-line offsets characteristic of standard interlaced timing standards (such as CEA-861 or VESA DMT).

Deinterlacing and Display Processing

Because liquid crystal and organic LED panels cannot display interlaced fields natively like cathode-ray tubes (CRTs) did, any interlaced signal traversing a DisplayPort cable must be converted:

  1. Sink-Side Deinterlacing: If the source GPU outputs raw interlaced fields over DisplayPort, the receiving monitor's internal scaler or scalar board must buffer the fields and apply a deinterlacing algorithm (such as bob, weave, or motion-adaptive deinterlacing) to reconstruct a progressive image.
  2. Source-Side Conversion: In most personal computing environments, modern operating systems and graphics drivers automatically deinterlace interlaced media prior to transmission. The GPU converts the interlaced source into a standard progressive signal, meaning the DisplayPort link operates purely in progressive mode, bypassing sink-side processing entirely.

Bandwidth and Efficiency Comparison

  • Bandwidth Usage: For a given refresh rate and resolution, interlaced video cuts the per-transmission pixel data in half compared to progressive video because only half the vertical lines are sent per cycle. However, modern DisplayPort bandwidth capabilities far exceed the requirements of legacy interlaced formats, making bandwidth savings negligible on current hardware.
  • Latency: Progressive transmission minimizes input latency because frames are displayed immediately upon arrival. Interlaced signals introduce processing latency at the display end, as the sink's processor must buffer consecutive fields before generating the final rendered frame.