How DisplayPort Handles Audio Clock Recovery

DisplayPort transmits uncompressed video and multi-channel digital audio over a shared set of high-speed differential serial lanes without dedicated hardware clock wires for any media stream. This article explains how the DisplayPort protocol achieves audio clock recovery at the sink device by embedding mathematical timestamp parameters—specifically \(M\) and \(N\) values—directly into the main link data stream, allowing the receiver’s internal Phase-Locked Loop (PLL) to synthesize the original audio sampling clock with high precision.

The Asynchronous Clock Problem

Traditional digital audio interfaces, such as I2S, utilize dedicated hardware lines to carry continuous word select and bit clock signals. DisplayPort eliminates dedicated clock wires entirely; both the main link bit clock and the audio clock must be reconstructed from the packetized serial stream.

Furthermore, the audio sampling rate (typically 32 kHz to 192 kHz) is fundamentally asynchronous to the fixed serial link rates of DisplayPort (such as 1.62 Gbps, 2.7 Gbps, 5.4 Gbps, or 8.1 Gbps). Because audio samples are packetized and transmitted in bursts during horizontal and vertical blanking intervals, the sink cannot determine the exact audio playback frequency merely by observing the arrival rate of the audio data packets.

The Fractional-N Clock Synthesis Model

DisplayPort resolves this discrepancy using a fractional-N frequency division scheme. The protocol establishes a direct mathematical relationship between the known DisplayPort link symbol clock (\(LS\_CLK\)) and the desired audio stream clock (\(f_{audio}\)).

This relationship is governed by the formula:

\[f_{audio} = LS\_CLK \times \frac{M_{aud}}{N_{aud}}\]

In this equation:

  • \(LS\_CLK\) is the link symbol clock frequency, which the sink hardware recovers directly from the incoming bitstream using its Clock and Data Recovery (CDR) unit.
  • \(M_{aud}\) (Audio Time Stamp value) is a dynamically calculated 24-bit integer representing the numerator.
  • \(N_{aud}\) (Audio Link Clock Divider) is a predetermined 24-bit integer representing the denominator, typically chosen based on the link rate to balance tracking speed and jitter.

Audio Clock Regeneration Packets

To relay these fractional values to the receiver, the DisplayPort source regularly injects Audio Stream Time Stamp (AUD_TIMESTAMP) packets into the link as Secondary Data Packets (SDP).

  1. Source Sampling: The source maintains a counter running on \(LS\_CLK\) and measures how many link clock cycles elapse over an exact number of audio clock periods, continuously updating the \(M_{aud}\) value to reflect any subtle drift or intentional frequency variations in the audio source.
  2. Packet Insertion: These timestamp packets are multiplexed into the main link alongside the Audio Stream (AUD_STREAM) packets, which contain the actual Pulse Code Modulation (PCM) or encoded audio data samples.
  3. Transmission Regularity: Timestamps are transmitted frequently enough to allow the receiver's tracking loop to react to clock drift and suppress low-frequency phase noise.

Sink-Side Audio Reconstruction Architecture

When the packetized data reaches the DisplayPort sink, the hardware uses a specialized pipeline to reconstruct a continuous, jitter-free audio clock:

  1. CDR Link Recovery: The sink's physical layer CDR locks onto the incoming serial data stream, extracting the raw data bits and recovering the underlying link clock (\(LS\_CLK\)).
  2. Packet Extraction: The link-layer decoder demultiplexes the secondary data packets, routing the audio sample payload to an elastic FIFO buffer and extracting the \(M_{aud}\) and \(N_{aud}\) values from the timestamp packets.
  3. Frequency Synthesis: The extracted \(M_{aud}\) and \(N_{aud}\) values, along with the recovered \(LS\_CLK\), are fed into an audio fractional-N Phase-Locked Loop (PLL) or a Digital Frequency Synthesizer. The PLL multiplies the link clock by the ratio \(M_{aud} / N_{aud}\) to regenerate the original audio master clock (often \(128 \times f_s\) or \(256 \times f_s\)).
  4. Buffer Management and Jitter Filtering: The elastic FIFO absorbs the bursty packet delivery from the DisplayPort link. The newly regenerated, continuous audio clock clocks the audio samples out of the FIFO into the digital-to-analog converter (DAC) or downstream audio processor at the exact native sampling rate, preventing buffer overflow or underflow.