DPCD Registers for Detecting Active LTTPRs

In modern DisplayPort architectures, Link Training Tunable PHY Repeaters (LTTPRs) are critical components used to maintain signal integrity over long transmission paths and complex board routing. To detect, configure, and monitor these retimers and redrivers, the DisplayPort Configuration Data (DPCD) space designates a dedicated memory map located between addresses F0000h and F02FFh. Examining specific registers within this range reveals the physical count, operational mode, capabilities, and real-time link training status of any active LTTPR in the signal chain.

LTTPR Identification and Discovery Registers

A DisplayPort Source determines whether LTTPR devices are present by reading the discovery block starting at base address F0000h.

  • LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV (F0000h): Reads the supported LTTPR architecture revision (e.g., 14h for DP 1.4, 20h for DP 2.0). A non-zero, valid read confirms that LTTPR functionality is supported along the path.
  • MAX_LINK_RATE_PHY_REPEATER (F0001h): Indicates the highest link transmission rate supported across the repeater chain (such as RBR, HBR, HBR2, HBR3, or UHBR speeds).
  • PHY_REPEATER_CNT (F0002h): Discloses the exact number of active physical repeaters present in the link. The architecture accommodates between 1 and 8 repeaters. A value of 00h signifies no LTTPR devices, while values between 01h and 08h identify the specific number of LTTPRs chained between the Source and Sink.
  • MAX_LANE_COUNT_PHY_REPEATER (F0004h): Defines the maximum lane count capability (1, 2, or 4 lanes) supported across the LTTPRs.

Mode Configuration and Control Registers

The behavior of the repeaters is managed through dedicated operational registers:

  • PHY_REPEATER_MODE (F0003h): Configures and indicates the operational state of the LTTPR chain. Writing or reading 55h sets the devices to Transparent Mode, where the repeaters do not actively participate in independent link training. A value of AAh indicates Non-Transparent Mode, where each repeater acts as an independent receiver and transmitter node for segmented link training.
  • PHY_REPEATER_EXTENDED_WAIT_TIMEOUT (F0005h): Specifies any extra latency or extended training timeouts required by slower PHY repeaters during the link training sequence.

When operating in Non-Transparent Mode, the Source executes link training on a hop-by-hop basis. The DPCD architecture maps dedicated status and setting blocks for each active repeater, assigned sequentially based on their position from the Sink back toward the Source (indexed LTTPR 1 through 8):

  • TRAINING_PATTERN_SET_PHY_REPEATER (F0010h onwards, indexed per repeater): Reflects the current training pattern (TPS1 through TPS4) applied to that specific repeater hop.
  • **TRAINING_LANE[0–3]_SET_PHY_REPEATER (F0011h–F0014h per repeater block):** Reflects the drive settings, such as voltage swing and pre-emphasis level requests, negotiated for each individual lane on that repeater hop.
  • LANE0_1_STATUS_PHY_REPEATER and LANE2_3_STATUS_PHY_REPEATER (F0030h–F0033h per repeater block): Diagnostic registers indicating the physical reception health of the repeater. These report bitfields identical to sink-side status registers:
    • Clock Recovery Done (CR_DONE): Confirms the repeater Phase-Locked Loop (PLL) has locked onto the incoming data stream.
    • Channel Equalization Done (EQ_DONE): Indicates equalizer convergence on the hop.
    • Symbol Locked: Confirms valid 8b/10b or 128b/132b framing synchronization.
  • LANE_ALIGN_STATUS_UPDATED_PHY_REPEATER (F0035h per repeater block): Confirms inter-lane deskew alignment across multi-lane configurations for that repeater.

By reading these diagnostic registers sequentially, diagnostic software or Source silicon can isolate specific signal integrity failures, identify the exact physical hop where link degradation occurs, and verify the health of every repeater segment independently.