DisplayPort Synchronous vs Asynchronous Clocking
This article provides an overview of the differences between synchronous and asynchronous clocking modes in DisplayPort links. It explores how pixel clocks relate to the high-speed main link clock, the mechanics of clock recovery using time-stamp values (\(M\) and \(N\)), and the practical engineering trade-offs regarding hardware design, flexibility, and signal integrity in modern display pipelines.
The DisplayPort Clocking Architecture
In a DisplayPort interface, digital audio/video data travels across high-speed differential lanes known as the Main Link. This transmission involves two distinct clock domains:
- Link Symbol Clock (\(LS\_CLK\)): The physical serial data rate clock used to transmit 8b/10b- or 128b/132b-encoded symbols across the physical lanes (e.g., RBR, HBR, HBR2, HBR3, UHBR).
- Stream Clock (\(Stream\_CLK\) or Pixel Clock): The rate at which active pixel data is processed and rendered by the source (GPU) and reconstructed by the sink (display panel).
Because the Main Link operates at fixed, standardized lane rates while video streams vary widely in resolution, color depth, and refresh rates, the receiver must reconstruct the original pixel clock from the link data. DisplayPort accommodates this via two distinct timing modes: Synchronous and Asynchronous.
Synchronous Clocking Mode
In synchronous clocking mode, the Stream Clock and the Link Symbol Clock are derived from the exact same master reference oscillator. Consequently, the two clocks maintain a fixed, mathematically locked phase and frequency relationship.
- Fixed Frequency Ratio: The relationship between the pixel clock (\(f_{stream}\)) and the link clock (\(f_{LS\_CLK}\)) is expressed as: \[\frac{f_{stream}}{f_{LS\_CLK}} = \frac{Mvid}{Nvid}\] In synchronous mode, the values of \(Mvid\) (Video Time Stamp \(M\)) and \(Nvid\) (Video Time Stamp \(N\)) are constant integers negotiated during link configuration and do not drift over time.
- Low Jitter and Simplified Recovery: Because both domains share a reference, there is no phase drift between the transmitter and receiver clocks. The sink device's Phase-Locked Loop (PLL) can regenerate the pixel clock with high stability and minimal tracking jitter.
- Limitations: Synchronous clocking requires tight hardware coupling at the source. Both the GPU display engine and the DisplayPort transmitter PHY must share a common frequency generation tree, reducing architectural flexibility.
Asynchronous Clocking Mode
In asynchronous clocking mode, the Stream Clock and the Link Symbol Clock originate from independent reference oscillators. There is no inherent phase alignment or fixed frequency relationship between the pixel generation pipeline and the high-speed serializer.
- Dynamic Time-Stamp Tracking (\(Mvid\) / \(Nvid\)): Because independent oscillators inevitably experience frequency drift due to thermal and manufacturing variations, the ratio between \(f_{stream}\) and \(f_{LS\_CLK}\) constantly shifts. To allow the sink to accurately recover the stream clock, the source continuously measures this ratio and transmits updated \(Mvid\) values within the Main Link framing overhead.
- Sink-Side Regeneration: The sink receiver uses the incoming, varying \(Mvid\) values alongside a static or fixed \(Nvid\) to dynamically steer its local Voltage-Controlled Oscillator (VCO) or Fractional-N PLL, continuously adjusting the reconstructed pixel clock to match the source.
- Higher Hardware Flexibility: Asynchronous mode allows system designers to decouple the display pipeline clock from the PHY interface clock entirely. This is essential for modern multi-source topologies, graphics cards with modular display controllers, and variable refresh rate architectures.
Key Technical Differences
| Feature | Synchronous Mode | Asynchronous Mode |
|---|---|---|
| Clock Source | Shared master oscillator for link and stream | Separate, independent oscillators |
| \(Mvid\) Behavior | Static / Fixed integer ratio | Dynamic; periodically updated in link overhead |
| Clock Drift | None; zero relative frequency drift | Present; compensated continuously by sink PLL |
| Sink PLL Requirements | Simpler tracking bandwidth; lower design overhead | Requires robust tracking PLL to handle modulation and drift |
| System Flexibility | Lower; imposes strict hardware layout rules | Higher; decoupled clock domains simplify system integration |
| Standard Support | Optional legacy mode in modern specifications | Default and standard mode across modern DP implementations |
Practical Implications in Modern Hardware
While early DisplayPort implementations provided synchronous clocking to reduce receiver bill-of-materials (BOM) costs and PLL complexity, modern hardware predominantly uses asynchronous clocking.
Asynchronous mode provides the design freedom necessary to support features such as Variable Refresh Rate (Adaptive-Sync), Multi-Stream Transport (MST) carrying multiple asynchronous streams over one physical link, and dynamic power states where link rates and pixel timings fluctuate independently. Modern receiver PHYs feature integrated, highly adaptable clock-data recovery (CDR) and PLL blocks capable of tracking asynchronous \(Mvid/Nvid\) streams with negligible jitter penalty.