DisplayPort SDP Structure in Framing Architecture

This article provides a technical overview of the Secondary Data Packet (SDP) structure within the DisplayPort framing architecture. It covers the placement of SDPs within the Main Link framing, the structural composition of SDP headers and payloads, error correction mechanisms, and the distribution of packet data across physical lanes.

Role of Secondary Data Packets in DisplayPort

In the DisplayPort protocol, the Main Link transports primary video streams alongside non-video data. Non-video information—including multi-channel audio, audio clock regeneration timestamps, CEA/CTA InfoFrames, Dynamic Range and Mastering metadata (HDR), and Visual Stream Configuration (VSC) packets—is encapsulated into Secondary Data Packets (SDPs).

SDPs are transmitted during the horizontal and vertical blanking intervals of the video stream. When no active video is being transmitted, or when utilizing stream multiplexing architectures like Multi-Stream Transport (MST), SDPs utilize the available link bandwidth efficiently without disrupting video pixel delivery.

SDP Framing and Delimiters

Within the 8b/10b physical layer framing, SDPs are framed using specific special control characters (K-codes):

  • Secondary-data Start (SS): Represented by the K28.2 control symbol. It signals the beginning of an SDP transmission to the sink device.
  • Secondary-data End (SE): Represented by the K28.5 control symbol. It marks the termination of the SDP.

In DisplayPort 2.0/2.1 utilizing 128b/132b channel coding, framing tokens integrated into the packet framing protocol replace raw K-codes, but the logical sequence of start, payload, and end indicators remains conceptually identical.

Structural Components of an SDP

A standard DisplayPort SDP consists of two primary sections: the Header and the Payload. The payload is further divided into up to four Sub-packets.

1. Header Architecture

The SDP header is four bytes wide (HB0 to HB3) and defines the packet type, structure, and operational characteristics:

  • HB0 (Packet Type): Defines the SDP category. Common types include:
    • 02h: Audio Stream Packet (ASP)
    • 04h: Audio Timestamp Packet (ATP)
    • 07h: Visual Stream Configuration (VSC) Packet
    • 8Xh: InfoFrames (e.g., Auxiliary Video Information, Dynamic HDR)
  • HB1 (Packet Specific / Sub-Type): Provides context specific to the packet type identified in HB0.
  • HB2 (Least Significant Byte of Payload Details): Indicates payload attributes, such as payload data length or specific sequence counters.
  • HB3 (Most Significant Byte of Payload Details): Carries additional parameter definitions, versioning, or reserved bits.

2. Header Error Correction (Header Parity)

Following the four header bytes, four Parity/ECC bytes (PB0 to PB3) are appended. The DisplayPort specification applies error-correcting code algorithms—typically BCH(15, 11) or simple parity generation depending on standard generation and link rates—enabling the receiver to detect multiple bit errors and correct single-bit errors in the packet header.

3. Payload and Sub-Packets

The SDP data payload generally accommodates up to 64 bytes of raw user data, organized into four distinct 16-byte sub-packets:

  • Sub-packet 0: Bytes 0–15
  • Sub-packet 1: Bytes 16–31
  • Sub-packet 2: Bytes 32–47
  • Sub-packet 3: Bytes 48–63

Each 16-byte sub-packet is paired with its own set of Parity/ECC bytes (typically 4 bytes of parity per sub-packet), ensuring localized data integrity verification. If an SDP requires fewer than 64 bytes of data, the unused sub-packets are marked invalid or filled with designated padding patterns.

Lane Mapping and Data Transmission

DisplayPort distributes data across 1, 2, or 4 physical Main Link lanes. SDP bytes are interleaved across all operational lanes immediately following the SS control symbol:

  • Single-Lane Configuration: Header bytes, parity bytes, sub-packets, and the trailing SE symbol are transmitted sequentially over Lane 0.
  • Two-Lane Configuration: Header and payload bytes alternate between Lane 0 and Lane 1 on a byte-by-byte basis.
  • Four-Lane Configuration: HB0 through HB3 are transmitted across Lanes 0 through 3 simultaneously in the first clock cycle. Subsequent clock cycles transmit the header parity, followed by the sub-packet data and ECC bytes across the 4-lane link.

Once the payload transmission and its associated error detection codes are fully dispatched, the source sends the SE delimiter across all active lanes to return the link to an idle or blanking state.